Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame^] | 3 | #include <cpu/x86/mtrr.h> |
| 4 | #include <cpu/x86/mp.h> |
| 5 | #include <amdblocks/cpu.h> |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 6 | #include <amdblocks/smm.h> |
| 7 | #include <console/console.h> |
| 8 | #include <cpu/amd/amd64_save_state.h> |
| 9 | #include <cpu/amd/msr.h> |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame^] | 10 | #include <cpu/amd/mtrr.h> |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 11 | #include <cpu/cpu.h> |
| 12 | #include <cpu/x86/msr.h> |
| 13 | #include <cpu/x86/smm.h> |
| 14 | #include <types.h> |
| 15 | |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame^] | 16 | /* AP MTRRs will be synced to the BSP in the SIPI vector so set them up before MP init. */ |
| 17 | static void pre_mp_init(void) |
| 18 | { |
| 19 | const msr_t syscfg = rdmsr(SYSCFG_MSR); |
| 20 | if (syscfg.lo & SYSCFG_MSR_TOM2WB) |
| 21 | x86_setup_mtrrs_with_detect_no_above_4gb(); |
| 22 | else |
| 23 | x86_setup_mtrrs_with_detect(); |
| 24 | x86_mtrr_check(); |
| 25 | } |
| 26 | |
| 27 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 28 | size_t *smm_save_state_size) |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 29 | { |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 30 | printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); |
| 31 | |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 32 | uintptr_t tseg_base; |
| 33 | size_t tseg_size; |
| 34 | |
| 35 | smm_region(&tseg_base, &tseg_size); |
| 36 | |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 37 | if (!IS_ALIGNED(tseg_base, tseg_size)) { |
| 38 | printk(BIOS_ERR, "TSEG base not aligned to TSEG size\n"); |
| 39 | return; |
| 40 | } |
| 41 | /* Minimum granularity for TSEG MSRs */ |
| 42 | if (tseg_size < 128 * KiB) { |
| 43 | printk(BIOS_ERR, "TSEG size (0x%zx) too small\n", tseg_size); |
| 44 | return; |
| 45 | } |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 46 | |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 47 | |
| 48 | smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); |
| 49 | *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); |
| 50 | } |
| 51 | |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame^] | 52 | static void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 53 | { |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 54 | amd64_smm_state_save_area_t *smm_state; |
| 55 | |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 56 | uintptr_t tseg_base; |
| 57 | size_t tseg_size; |
| 58 | |
| 59 | smm_region(&tseg_base, &tseg_size); |
| 60 | |
| 61 | msr_t msr; |
| 62 | msr.lo = tseg_base; |
| 63 | msr.hi = 0; |
| 64 | wrmsr(SMM_ADDR_MSR, msr); |
| 65 | |
| 66 | msr.lo = ~(tseg_size - 1); |
| 67 | msr.lo |= SMM_TSEG_WB; |
| 68 | msr.hi = (1 << (cpu_phys_address_size() - 32)) - 1; |
| 69 | wrmsr(SMM_MASK_MSR, msr); |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 70 | |
| 71 | smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); |
| 72 | smm_state->smbase = staggered_smbase; |
| 73 | } |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame^] | 74 | |
| 75 | const struct mp_ops amd_mp_ops_with_smm = { |
| 76 | .pre_mp_init = pre_mp_init, |
| 77 | .get_cpu_count = get_cpu_count, |
| 78 | .get_smm_info = get_smm_info, |
| 79 | .relocation_handler = smm_relocation_handler, |
| 80 | .post_mp_init = global_smi_enable, |
| 81 | }; |