Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 17 | #include "chip.h" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 21 | #include <device/pci_ops.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | #include <device/pciexp.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <reg_script.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 25 | #include <soc/pci_devs.h> |
| 26 | #include <soc/pcie.h> |
| 27 | #include <soc/ramstage.h> |
| 28 | #include <soc/smm.h> |
| 29 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | static int pll_en_off; |
| 31 | static uint32_t strpfusecfg; |
| 32 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 33 | static inline int root_port_offset(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 34 | { |
| 35 | return PCI_FUNC(dev->path.pci.devfn); |
| 36 | } |
| 37 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 38 | static inline int is_first_port(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 39 | { |
| 40 | return root_port_offset(dev) == PCIE_PORT1_FUNC; |
| 41 | } |
| 42 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 43 | static void pcie_init(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 44 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 45 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 46 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 47 | } |
| 48 | |
| 49 | static const struct reg_script no_dev_behind_port[] = { |
| 50 | REG_PCI_OR32(PCIEALC, (1 << 26)), |
| 51 | REG_PCI_POLL32(PCIESTS1, 0x1f000000, (1 << 24), 50000), |
| 52 | REG_PCI_OR32(PHYCTL4, SQDIS), |
| 53 | REG_SCRIPT_END, |
| 54 | }; |
| 55 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 56 | static void check_port_enabled(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 57 | { |
| 58 | int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; |
| 59 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 60 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 61 | __FILE__, __func__, dev_name(dev)); |
| 62 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 63 | switch (root_port_offset(dev)) { |
| 64 | case PCIE_PORT1_FUNC: |
| 65 | /* Port 1 cannot be disabled from strapping config. */ |
| 66 | break; |
| 67 | case PCIE_PORT2_FUNC: |
| 68 | /* Port 2 disabled in all configs but 4x1. */ |
| 69 | if (rp_config != 0x0) |
| 70 | dev->enabled = 0; |
| 71 | break; |
| 72 | case PCIE_PORT3_FUNC: |
| 73 | /* Port 3 disabled only in 1x4 config. */ |
| 74 | if (rp_config == 0x3) |
| 75 | dev->enabled = 0; |
| 76 | break; |
| 77 | case PCIE_PORT4_FUNC: |
| 78 | /* Port 4 disabled in 1x4 and 2x2 config. */ |
| 79 | if (rp_config >= 0x2) |
| 80 | dev->enabled = 0; |
| 81 | break; |
| 82 | } |
| 83 | } |
| 84 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 85 | static void check_device_present(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 86 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 87 | /* port1_dev will store the dev struct pointer of the PORT1 */ |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 88 | static struct device *port1_dev; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 89 | |
| 90 | /* |
| 91 | * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. |
| 92 | * For each port initial assumption is that, each port will have |
| 93 | * devices connected to it. Later we will scan each PORT and if |
| 94 | * the device is not attached to that port we will update |
| 95 | * rootports_in_use. If none of the root port is in use we will |
| 96 | * disable PORT1 otherwise we will keep PORT1 enabled per spec. |
| 97 | * In future if the Soc has more number of PCIe Root ports then |
| 98 | * change MAX_ROOT_PORTS_BSW value accordingly. |
| 99 | */ |
| 100 | |
| 101 | static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; |
| 102 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 103 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 104 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 105 | /* Set slot implemented. */ |
| 106 | pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); |
| 107 | |
| 108 | /* No device present. */ |
| 109 | if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 110 | rootports_in_use--; |
| 111 | printk(BIOS_DEBUG, "No PCIe device present."); |
| 112 | |
| 113 | /* |
| 114 | * Defer PORT1 disabling for now. When we are at Last port |
| 115 | * we will check rootports_in_use and disable PORT1 if none |
| 116 | * of the port has any device connected |
| 117 | */ |
| 118 | if (!is_first_port(dev)) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 119 | reg_script_run_on_dev(dev, no_dev_behind_port); |
| 120 | dev->enabled = 0; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 121 | } else |
| 122 | port1_dev = dev; |
| 123 | /* |
| 124 | * If none of the ROOT PORT has devices connected then |
| 125 | * disable PORT1 else keep the PORT1 enable |
| 126 | */ |
| 127 | if (!rootports_in_use) { |
| 128 | reg_script_run_on_dev(port1_dev, no_dev_behind_port); |
| 129 | port1_dev->enabled = 0; |
| 130 | southcluster_enable_dev(port1_dev); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 131 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 132 | } else if (!dev->enabled) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 133 | /* Port is disabled, but device present. Disable link. */ |
| 134 | pci_write_config32(dev, LCTL, |
| 135 | pci_read_config32(dev, LCTL) | LD); |
| 136 | } |
| 137 | } |
| 138 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 139 | static void pcie_enable(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 140 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 141 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 142 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 143 | if (is_first_port(dev)) { |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame^] | 144 | struct soc_intel_braswell_config *config = config_of(dev); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 145 | uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); |
| 146 | pll_en_off = !!(reg & PLL_OFF_EN); |
| 147 | |
| 148 | strpfusecfg = pci_read_config32(dev, STRPFUSECFG); |
| 149 | |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame^] | 150 | if (config->pcie_wake_enable) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 151 | southcluster_smm_save_param( |
| 152 | SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); |
| 153 | } |
| 154 | |
| 155 | /* Check if device is enabled in strapping. */ |
| 156 | check_port_enabled(dev); |
| 157 | /* Determine if device is behind port. */ |
| 158 | check_device_present(dev); |
| 159 | |
| 160 | southcluster_enable_dev(dev); |
| 161 | } |
| 162 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 163 | static struct pci_operations pcie_root_ops = { |
Kyösti Mälkki | 2520032 | 2019-03-20 18:36:37 +0200 | [diff] [blame] | 164 | .set_subsystem = pci_dev_set_subsystem, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 165 | }; |
| 166 | |
| 167 | static struct device_operations device_ops = { |
| 168 | .read_resources = pci_bus_read_resources, |
| 169 | .set_resources = pci_dev_set_resources, |
| 170 | .enable_resources = pci_bus_enable_resources, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 171 | .init = pcie_init, |
| 172 | .scan_bus = pciexp_scan_bridge, |
| 173 | .enable = pcie_enable, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 174 | .ops_pci = &pcie_root_ops, |
| 175 | }; |
| 176 | |
| 177 | static const unsigned short pci_device_ids[] = { |
| 178 | PCIE_PORT1_DEVID, PCIE_PORT2_DEVID, PCIE_PORT3_DEVID, PCIE_PORT4_DEVID, |
| 179 | 0 |
| 180 | }; |
| 181 | |
| 182 | static const struct pci_driver pcie_root_ports __pci_driver = { |
| 183 | .ops = &device_ops, |
| 184 | .vendor = PCI_VENDOR_ID_INTEL, |
| 185 | .devices = pci_device_ids, |
| 186 | }; |