Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | 25509ee | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 19 | */ |
| 20 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 21 | #include "chip.h" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pciexp.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <reg_script.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 28 | #include <soc/pci_devs.h> |
| 29 | #include <soc/pcie.h> |
| 30 | #include <soc/ramstage.h> |
| 31 | #include <soc/smm.h> |
| 32 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | static int pll_en_off; |
| 34 | static uint32_t strpfusecfg; |
| 35 | |
| 36 | static inline int root_port_offset(device_t dev) |
| 37 | { |
| 38 | return PCI_FUNC(dev->path.pci.devfn); |
| 39 | } |
| 40 | |
| 41 | static inline int is_first_port(device_t dev) |
| 42 | { |
| 43 | return root_port_offset(dev) == PCIE_PORT1_FUNC; |
| 44 | } |
| 45 | |
| 46 | static const struct reg_script init_static_before_exit_latency[] = { |
| 47 | /* Disable optimized buffer flush fill and latency tolerant reporting */ |
| 48 | REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0), |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 49 | REG_PCI_RMW32(DSTS2, ~(OBFFEN | LTRME), 0), |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 50 | /* Set maximum payload size. */ |
| 51 | REG_PCI_RMW32(DCAP, ~MPS_MASK, 0), |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 52 | /* |
| 53 | * Disable transmit datapath flush timer, clear transmit config change |
| 54 | * wait time, clear sideband interface idle counter. |
| 55 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 56 | REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0), |
| 57 | REG_SCRIPT_END, |
| 58 | }; |
| 59 | |
| 60 | static const struct reg_script init_static_after_exit_latency[] = { |
| 61 | /* Set common clock configuration. */ |
| 62 | REG_PCI_OR16(LCTL, CCC), |
| 63 | /* Set NFTS to 0x743a361b */ |
| 64 | REG_PCI_WRITE32(NFTS, 0x743a361b), |
| 65 | /* Set common clock latency to 0x3 */ |
| 66 | REG_PCI_RMW32(MPC, ~CCEL_MASK, (0x3 << CCEL_SHIFT)), |
| 67 | /* Set relay timer policy. */ |
| 68 | REG_PCI_RMW32(RTP, 0xff000000, 0x854c74), |
| 69 | /* Set IOSF packet fast transmit mode and link speed training policy. */ |
| 70 | REG_PCI_OR16(MPC2, IPF | LSTP), |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 71 | /* |
| 72 | * Channel configuration - enable upstream posted split, set non-posted |
| 73 | * and posted request size |
| 74 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 75 | REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS), |
| 76 | /* Completion status replay enable and set TLP grant count */ |
| 77 | REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)), |
| 78 | /* Assume no IOAPIC behind root port -- disable EOI forwarding. */ |
| 79 | REG_PCI_OR16(MPC2, EOIFD), |
| 80 | /* Expose AER */ |
| 81 | REG_PCI_RMW32(AERCH, ~0, (1 << 16) | (1 << 0)), |
| 82 | /* set completion timeout to 160ms to 170ms */ |
| 83 | REG_PCI_RMW16(DSTS2, ~CTD, 0x6), |
| 84 | /* Enable AER */ |
| 85 | REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 86 | /* Read and write back capabaility registers. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 87 | REG_PCI_OR32(0x34, 0), |
| 88 | REG_PCI_OR32(0x80, 0), |
| 89 | /* Retrain the link. */ |
| 90 | REG_PCI_OR16(LCTL, RL), |
| 91 | REG_SCRIPT_END, |
| 92 | }; |
| 93 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 94 | static void pcie_init(device_t dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 95 | { |
| 96 | struct reg_script init_script[] = { |
| 97 | REG_SCRIPT_NEXT(init_static_before_exit_latency), |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 98 | /* |
| 99 | * Exit latency configuration based on |
| 100 | * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1 |
| 101 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 102 | REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 103 | 2 << (L1EXIT_MASK + pll_en_off)), |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 104 | REG_SCRIPT_NEXT(init_static_after_exit_latency), |
| 105 | /* Disable hot plug, set power to 10W, set slot number. */ |
| 106 | REG_PCI_RMW32(SLCAP, ~(HPC | HPS), |
| 107 | (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | |
| 108 | (root_port_offset(dev) << SLN_SHIFT)), |
| 109 | /* Dynamic clock gating. */ |
| 110 | REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN), |
| 111 | REG_PCI_OR32(PWRCTL, RPL1SQPOL | RPDTSQPOL), |
| 112 | REG_PCI_OR32(PCIEDBG, SPCE), |
| 113 | REG_SCRIPT_END, |
| 114 | }; |
| 115 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 116 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 117 | __FILE__, __func__, dev_name(dev)); |
| 118 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 119 | reg_script_run_on_dev(dev, init_script); |
| 120 | |
| 121 | if (is_first_port(dev)) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 122 | struct soc_intel_braswell_config *config = dev->chip_info; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 123 | uint32_t reg = pci_read_config32(dev, RPPGEN); |
| 124 | reg |= SRDLCGEN | SRDBCGEN; |
| 125 | |
| 126 | if (config && config->clkreq_enable) |
| 127 | reg |= LCLKREQEN | BBCLKREQEN; |
| 128 | |
| 129 | pci_write_config32(dev, RPPGEN, reg); |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | static const struct reg_script no_dev_behind_port[] = { |
| 134 | REG_PCI_OR32(PCIEALC, (1 << 26)), |
| 135 | REG_PCI_POLL32(PCIESTS1, 0x1f000000, (1 << 24), 50000), |
| 136 | REG_PCI_OR32(PHYCTL4, SQDIS), |
| 137 | REG_SCRIPT_END, |
| 138 | }; |
| 139 | |
| 140 | static void check_port_enabled(device_t dev) |
| 141 | { |
| 142 | int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; |
| 143 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 144 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 145 | __FILE__, __func__, dev_name(dev)); |
| 146 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 147 | switch (root_port_offset(dev)) { |
| 148 | case PCIE_PORT1_FUNC: |
| 149 | /* Port 1 cannot be disabled from strapping config. */ |
| 150 | break; |
| 151 | case PCIE_PORT2_FUNC: |
| 152 | /* Port 2 disabled in all configs but 4x1. */ |
| 153 | if (rp_config != 0x0) |
| 154 | dev->enabled = 0; |
| 155 | break; |
| 156 | case PCIE_PORT3_FUNC: |
| 157 | /* Port 3 disabled only in 1x4 config. */ |
| 158 | if (rp_config == 0x3) |
| 159 | dev->enabled = 0; |
| 160 | break; |
| 161 | case PCIE_PORT4_FUNC: |
| 162 | /* Port 4 disabled in 1x4 and 2x2 config. */ |
| 163 | if (rp_config >= 0x2) |
| 164 | dev->enabled = 0; |
| 165 | break; |
| 166 | } |
| 167 | } |
| 168 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 169 | static void check_device_present(device_t dev) |
| 170 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 171 | /* port1_dev will store the dev struct pointer of the PORT1 */ |
| 172 | static device_t port1_dev; |
| 173 | |
| 174 | /* |
| 175 | * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. |
| 176 | * For each port initial assumption is that, each port will have |
| 177 | * devices connected to it. Later we will scan each PORT and if |
| 178 | * the device is not attached to that port we will update |
| 179 | * rootports_in_use. If none of the root port is in use we will |
| 180 | * disable PORT1 otherwise we will keep PORT1 enabled per spec. |
| 181 | * In future if the Soc has more number of PCIe Root ports then |
| 182 | * change MAX_ROOT_PORTS_BSW value accordingly. |
| 183 | */ |
| 184 | |
| 185 | static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; |
| 186 | |
| 187 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 188 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 189 | /* Set slot implemented. */ |
| 190 | pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); |
| 191 | |
| 192 | /* No device present. */ |
| 193 | if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 194 | rootports_in_use--; |
| 195 | printk(BIOS_DEBUG, "No PCIe device present."); |
| 196 | |
| 197 | /* |
| 198 | * Defer PORT1 disabling for now. When we are at Last port |
| 199 | * we will check rootports_in_use and disable PORT1 if none |
| 200 | * of the port has any device connected |
| 201 | */ |
| 202 | if (!is_first_port(dev)) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 203 | reg_script_run_on_dev(dev, no_dev_behind_port); |
| 204 | dev->enabled = 0; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 205 | } else |
| 206 | port1_dev = dev; |
| 207 | /* |
| 208 | * If none of the ROOT PORT has devices connected then |
| 209 | * disable PORT1 else keep the PORT1 enable |
| 210 | */ |
| 211 | if (!rootports_in_use) { |
| 212 | reg_script_run_on_dev(port1_dev, no_dev_behind_port); |
| 213 | port1_dev->enabled = 0; |
| 214 | southcluster_enable_dev(port1_dev); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 215 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 216 | } else if (!dev->enabled) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 217 | /* Port is disabled, but device present. Disable link. */ |
| 218 | pci_write_config32(dev, LCTL, |
| 219 | pci_read_config32(dev, LCTL) | LD); |
| 220 | } |
| 221 | } |
| 222 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 223 | static void pcie_enable(device_t dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 224 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 225 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 226 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 227 | if (is_first_port(dev)) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 228 | struct soc_intel_braswell_config *config = dev->chip_info; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 229 | uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); |
| 230 | pll_en_off = !!(reg & PLL_OFF_EN); |
| 231 | |
| 232 | strpfusecfg = pci_read_config32(dev, STRPFUSECFG); |
| 233 | |
| 234 | if (config && config->pcie_wake_enable) |
| 235 | southcluster_smm_save_param( |
| 236 | SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); |
| 237 | } |
| 238 | |
| 239 | /* Check if device is enabled in strapping. */ |
| 240 | check_port_enabled(dev); |
| 241 | /* Determine if device is behind port. */ |
| 242 | check_device_present(dev); |
| 243 | |
| 244 | southcluster_enable_dev(dev); |
| 245 | } |
| 246 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 247 | static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) |
| 248 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 249 | printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", |
| 250 | __FILE__, __func__, dev_name(dev), vid, did); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 251 | uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); |
| 252 | |
| 253 | if (!didvid) |
| 254 | didvid = pci_read_config32(dev, PCI_VENDOR_ID); |
| 255 | pci_write_config32(dev, 0x94, didvid); |
| 256 | } |
| 257 | |
| 258 | static struct pci_operations pcie_root_ops = { |
| 259 | .set_subsystem = &pcie_root_set_subsystem, |
| 260 | }; |
| 261 | |
| 262 | static struct device_operations device_ops = { |
| 263 | .read_resources = pci_bus_read_resources, |
| 264 | .set_resources = pci_dev_set_resources, |
| 265 | .enable_resources = pci_bus_enable_resources, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame^] | 266 | .init = pcie_init, |
| 267 | .scan_bus = pciexp_scan_bridge, |
| 268 | .enable = pcie_enable, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 269 | .ops_pci = &pcie_root_ops, |
| 270 | }; |
| 271 | |
| 272 | static const unsigned short pci_device_ids[] = { |
| 273 | PCIE_PORT1_DEVID, PCIE_PORT2_DEVID, PCIE_PORT3_DEVID, PCIE_PORT4_DEVID, |
| 274 | 0 |
| 275 | }; |
| 276 | |
| 277 | static const struct pci_driver pcie_root_ports __pci_driver = { |
| 278 | .ops = &device_ops, |
| 279 | .vendor = PCI_VENDOR_ID_INTEL, |
| 280 | .devices = pci_device_ids, |
| 281 | }; |