Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <console/usb.h> |
| 18 | #include <bootmode.h> |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 19 | #include <cf9_reset.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 20 | #include <string.h> |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 21 | #include <device/device.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 23 | #include <arch/cpu.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 24 | #include <cbmem.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 25 | #include <cbfs.h> |
| 26 | #include <ip_checksum.h> |
| 27 | #include <pc80/mc146818rtc.h> |
| 28 | #include <device/pci_def.h> |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 29 | #include <lib.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 30 | #include <mrc_cache.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 31 | #include <timestamp.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 32 | #include "raminit.h" |
| 33 | #include "pei_data.h" |
| 34 | #include "sandybridge.h" |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 35 | #include "chip.h" |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 36 | #include <security/vboot/vboot_common.h> |
Patrick Georgi | 27fbbcf | 2019-04-23 12:33:23 +0200 | [diff] [blame] | 37 | #include <southbridge/intel/bd82x6x/pch.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 38 | |
| 39 | /* Management Engine is in the southbridge */ |
Elyes HAOUAS | 21b71ce6 | 2018-06-16 18:43:52 +0200 | [diff] [blame] | 40 | #include <southbridge/intel/bd82x6x/me.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 41 | |
| 42 | /* |
| 43 | * MRC scrambler seed offsets should be reserved in |
| 44 | * mainboard cmos.layout and not covered by checksum. |
| 45 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 46 | #if CONFIG(USE_OPTION_TABLE) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 47 | #include "option_table.h" |
| 48 | #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) |
| 49 | #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) |
| 50 | #define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) |
| 51 | #else |
| 52 | #define CMOS_OFFSET_MRC_SEED 152 |
| 53 | #define CMOS_OFFSET_MRC_SEED_S3 156 |
| 54 | #define CMOS_OFFSET_MRC_SEED_CHK 160 |
| 55 | #endif |
| 56 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 57 | #define MRC_CACHE_VERSION 0 |
| 58 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 59 | void save_mrc_data(struct pei_data *pei_data) |
| 60 | { |
| 61 | u16 c1, c2, checksum; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 62 | |
| 63 | /* Save the MRC S3 restore data to cbmem */ |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 64 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, |
| 65 | pei_data->mrc_output, |
| 66 | pei_data->mrc_output_len); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 67 | |
| 68 | /* Save the MRC seed values to CMOS */ |
Kyösti Mälkki | 2879107 | 2020-01-04 12:58:53 +0200 | [diff] [blame] | 69 | cmos_write32(pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 70 | printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 71 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 72 | |
Kyösti Mälkki | 2879107 | 2020-01-04 12:58:53 +0200 | [diff] [blame] | 73 | cmos_write32(pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 75 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 76 | |
| 77 | /* Save a simple checksum of the seed values */ |
| 78 | c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, |
| 79 | sizeof(u32)); |
| 80 | c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, |
| 81 | sizeof(u32)); |
| 82 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 83 | |
| 84 | cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); |
| 85 | cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); |
| 86 | } |
| 87 | |
| 88 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 89 | { |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 90 | struct region_device rdev; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 91 | u16 c1, c2, checksum, seed_checksum; |
| 92 | |
| 93 | // preset just in case there is an error |
| 94 | pei_data->mrc_input = NULL; |
| 95 | pei_data->mrc_input_len = 0; |
| 96 | |
| 97 | /* Read scrambler seeds from CMOS */ |
| 98 | pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); |
| 99 | printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 100 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 101 | |
| 102 | pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); |
| 103 | printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 104 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 105 | |
| 106 | /* Compute seed checksum and compare */ |
| 107 | c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, |
| 108 | sizeof(u32)); |
| 109 | c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, |
| 110 | sizeof(u32)); |
| 111 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 112 | |
| 113 | seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); |
| 114 | seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; |
| 115 | |
| 116 | if (checksum != seed_checksum) { |
| 117 | printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); |
| 118 | pei_data->scrambler_seed = 0; |
| 119 | pei_data->scrambler_seed_s3 = 0; |
| 120 | return; |
| 121 | } |
| 122 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 123 | if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, |
| 124 | &rdev)) { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 125 | /* error message printed in find_current_mrc_cache */ |
| 126 | return; |
| 127 | } |
| 128 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 129 | pei_data->mrc_input = rdev_mmap_full(&rdev); |
| 130 | pei_data->mrc_input_len = region_device_sz(&rdev); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 131 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 132 | printk(BIOS_DEBUG, "%s: at %p, size %x\n", |
| 133 | __func__, pei_data->mrc_input, pei_data->mrc_input_len); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 134 | } |
| 135 | |
Elyes HAOUAS | 448d9fb | 2018-05-22 12:51:27 +0200 | [diff] [blame] | 136 | static const char *ecc_decoder[] = { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 137 | "inactive", |
| 138 | "active on IO", |
| 139 | "disabled on IO", |
| 140 | "active" |
| 141 | }; |
| 142 | |
| 143 | /* |
| 144 | * Dump in the log memory controller configuration as read from the memory |
| 145 | * controller registers. |
| 146 | */ |
| 147 | static void report_memory_config(void) |
| 148 | { |
| 149 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 150 | int i; |
| 151 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 152 | addr_decoder_common = MCHBAR32(MAD_CHNL); |
| 153 | addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); |
| 154 | addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 155 | |
| 156 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
Angel Pons | 3473f76 | 2019-12-31 14:26:23 +0100 | [diff] [blame] | 157 | (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50)/100); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 158 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 159 | addr_decoder_common & 3, |
| 160 | (addr_decoder_common >> 2) & 3, |
| 161 | (addr_decoder_common >> 4) & 3); |
| 162 | |
| 163 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 164 | u32 ch_conf = addr_decode_ch[i]; |
| 165 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", |
| 166 | i, ch_conf); |
| 167 | printk(BIOS_DEBUG, " ECC %s\n", |
| 168 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 169 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 170 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 171 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 172 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 173 | printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", |
| 174 | ((ch_conf >> 0) & 0xff) * 256, |
| 175 | ((ch_conf >> 19) & 1) ? 16 : 8, |
| 176 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 177 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 178 | printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", |
| 179 | ((ch_conf >> 8) & 0xff) * 256, |
| 180 | ((ch_conf >> 20) & 1) ? 16 : 8, |
| 181 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 182 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 183 | } |
| 184 | } |
| 185 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 186 | /** |
| 187 | * Find PEI executable in coreboot filesystem and execute it. |
| 188 | * |
| 189 | * @param pei_data: configuration data for UEFI PEI reference code |
| 190 | */ |
| 191 | void sdram_initialize(struct pei_data *pei_data) |
| 192 | { |
| 193 | struct sys_info sysinfo; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 194 | int (*entry) (struct pei_data *pei_data) __attribute__((regparm(1))); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 195 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 196 | /* Wait for ME to be ready */ |
| 197 | intel_early_me_init(); |
| 198 | intel_early_me_uma_size(); |
| 199 | |
| 200 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 201 | |
| 202 | memset(&sysinfo, 0, sizeof(sysinfo)); |
| 203 | |
| 204 | sysinfo.boot_path = pei_data->boot_mode; |
| 205 | |
| 206 | /* |
| 207 | * Do not pass MRC data in for recovery mode boot, |
| 208 | * Always pass it in for S3 resume. |
| 209 | */ |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 210 | if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 211 | prepare_mrc_cache(pei_data); |
| 212 | |
| 213 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 214 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
| 215 | printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 216 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | /* Pass console handler in pei_data */ |
| 220 | pei_data->tx_byte = do_putchar; |
| 221 | |
| 222 | /* Locate and call UEFI System Agent binary. */ |
| 223 | entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); |
| 224 | if (entry) { |
| 225 | int rv; |
| 226 | rv = entry (pei_data); |
| 227 | if (rv) { |
| 228 | switch (rv) { |
| 229 | case -1: |
| 230 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 231 | break; |
| 232 | case -2: |
| 233 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 234 | break; |
| 235 | default: |
| 236 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 237 | } |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 238 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 239 | "Nonzero MRC return value.\n"); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 240 | } |
| 241 | } else { |
| 242 | die("UEFI PEI System Agent not found.\n"); |
| 243 | } |
| 244 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 245 | /* mrc.bin reconfigures USB, so reinit it to have debug */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 246 | if (CONFIG(USBDEBUG_IN_PRE_RAM)) |
Kyösti Mälkki | 63649d2 | 2018-12-29 09:40:40 +0200 | [diff] [blame] | 247 | usbdebug_hw_init(true); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 248 | |
| 249 | /* For reference print the System Agent version |
| 250 | * after executing the UEFI PEI stage. |
| 251 | */ |
| 252 | u32 version = MCHBAR32(0x5034); |
| 253 | printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 254 | version >> 24, (version >> 16) & 0xff, |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 255 | (version >> 8) & 0xff, version & 0xff); |
| 256 | |
| 257 | /* Send ME init done for SandyBridge here. This is done |
| 258 | * inside the SystemAgent binary on IvyBridge. */ |
| 259 | if (BASE_REV_SNB == |
| 260 | (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) |
| 261 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 262 | else |
| 263 | intel_early_me_status(); |
| 264 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 265 | report_memory_config(); |
| 266 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 267 | |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 268 | /* These are the location and structure of MRC_VAR data in CAR. |
| 269 | The CAR region looks like this: |
| 270 | +------------------+ -> DCACHE_RAM_BASE |
| 271 | | | |
| 272 | | | |
| 273 | | COREBOOT STACK | |
| 274 | | | |
| 275 | | | |
| 276 | +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 277 | | | |
| 278 | | MRC HEAP | |
| 279 | | size = 0x5000 | |
| 280 | | | |
| 281 | +------------------+ |
| 282 | | | |
| 283 | | MRC VAR | |
| 284 | | size = 0x4000 | |
| 285 | | | |
| 286 | +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE |
| 287 | + DCACHE_RAM_MRC_VAR_SIZE |
| 288 | |
| 289 | */ |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 290 | #define DCACHE_RAM_MRC_VAR_BASE \ |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 291 | (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + \ |
| 292 | CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000) |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 293 | |
| 294 | struct mrc_var_data { |
| 295 | u32 acpi_timer_flag; |
| 296 | u32 pool_used; |
| 297 | u32 pool_base; |
| 298 | u32 tx_byte; |
| 299 | u32 reserved[4]; |
| 300 | } __packed; |
| 301 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 302 | static void northbridge_fill_pei_data(struct pei_data *pei_data) |
| 303 | { |
| 304 | pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; |
| 305 | pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; |
| 306 | pei_data->epbar = DEFAULT_EPBAR; |
| 307 | pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; |
| 308 | pei_data->hpet_address = CONFIG_HPET_ADDRESS; |
| 309 | pei_data->thermalbase = 0xfed08000; |
| 310 | pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; |
| 311 | pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; |
| 312 | |
| 313 | if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { |
| 314 | const struct device *dev = pcidev_on_root(1, 0); |
| 315 | pei_data->pcie_init = dev && dev->enabled; |
| 316 | } else { |
| 317 | pei_data->pcie_init = 0; |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | static void southbridge_fill_pei_data(struct pei_data *pei_data) |
| 322 | { |
| 323 | const struct device *dev = pcidev_on_root(0x19, 0); |
| 324 | |
| 325 | pei_data->smbusbar = SMBUS_IO_BASE; |
| 326 | pei_data->wdbbar = 0x4000000; |
| 327 | pei_data->wdbsize = 0x1000; |
| 328 | pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; |
| 329 | pei_data->pmbase = DEFAULT_PMBASE; |
| 330 | pei_data->gpiobase = DEFAULT_GPIOBASE; |
| 331 | pei_data->gbe_enable = dev && dev->enabled; |
| 332 | } |
| 333 | |
| 334 | static void devicetree_fill_pei_data(struct pei_data *pei_data) |
| 335 | { |
| 336 | const struct northbridge_intel_sandybridge_config *cfg; |
| 337 | |
| 338 | const struct device *dev = pcidev_on_root(0, 0); |
| 339 | if (!dev || !dev->chip_info) |
| 340 | return; |
| 341 | |
| 342 | cfg = dev->chip_info; |
| 343 | |
| 344 | switch (cfg->max_mem_clock_mhz) { |
| 345 | /* MRC only supports fixed numbers of frequencies */ |
| 346 | default: |
| 347 | printk(BIOS_WARNING, "RAMINIT: Limiting DDR3 clock to 800 Mhz\n"); |
| 348 | /* fallthrough */ |
| 349 | case 400: |
| 350 | pei_data->max_ddr3_freq = 800; |
| 351 | break; |
| 352 | case 533: |
| 353 | pei_data->max_ddr3_freq = 1066; |
| 354 | break; |
| 355 | case 666: |
| 356 | pei_data->max_ddr3_freq = 1333; |
| 357 | break; |
| 358 | case 800: |
| 359 | pei_data->max_ddr3_freq = 1600; |
| 360 | break; |
| 361 | |
| 362 | } |
| 363 | |
| 364 | memcpy(pei_data->spd_addresses, cfg->spd_addresses, |
| 365 | sizeof(pei_data->spd_addresses)); |
| 366 | |
| 367 | memcpy(pei_data->ts_addresses, cfg->ts_addresses, |
| 368 | sizeof(pei_data->ts_addresses)); |
| 369 | |
| 370 | pei_data->ec_present = cfg->ec_present; |
| 371 | pei_data->ddr3lv_support = cfg->ddr3lv_support; |
| 372 | |
| 373 | pei_data->nmode = cfg->nmode; |
| 374 | pei_data->ddr_refresh_rate_config = cfg->ddr_refresh_rate_config; |
| 375 | |
| 376 | memcpy(pei_data->usb_port_config, cfg->usb_port_config, |
| 377 | sizeof(pei_data->usb_port_config)); |
| 378 | |
| 379 | pei_data->usb3.mode = cfg->usb3.mode; |
| 380 | pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; |
| 381 | pei_data->usb3.preboot_support = cfg->usb3.preboot_support; |
| 382 | pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; |
| 383 | } |
| 384 | |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 385 | static void disable_p2p(void) |
| 386 | { |
| 387 | /* Disable PCI-to-PCI bridge early to prevent probing by MRC. */ |
| 388 | const struct device *const p2p = pcidev_on_root(0x1e, 0); |
| 389 | if (p2p && p2p->enabled) |
| 390 | return; |
| 391 | |
| 392 | RCBA32(FD) |= PCH_DISABLE_P2P; |
| 393 | } |
| 394 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 395 | void perform_raminit(int s3resume) |
| 396 | { |
| 397 | int cbmem_was_initted; |
| 398 | struct pei_data pei_data; |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 399 | struct mrc_var_data *mrc_var; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 400 | |
| 401 | /* Prepare USB controller early in S3 resume */ |
| 402 | if (!mainboard_should_reset_usb(s3resume)) |
| 403 | enable_usb_bar(); |
| 404 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 405 | memset(&pei_data, 0, sizeof(pei_data)); |
| 406 | pei_data.pei_version = PEI_VERSION, |
| 407 | |
| 408 | northbridge_fill_pei_data(&pei_data); |
| 409 | southbridge_fill_pei_data(&pei_data); |
| 410 | devicetree_fill_pei_data(&pei_data); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 411 | mainboard_fill_pei_data(&pei_data); |
| 412 | |
| 413 | post_code(0x3a); |
Patrick Rudolph | 59b4255 | 2019-05-08 12:44:15 +0200 | [diff] [blame] | 414 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 415 | /* Fill after mainboard_fill_pei_data as it might provide spd_data */ |
| 416 | pei_data.dimm_channel0_disabled = |
| 417 | (!pei_data.spd_addresses[0] && !pei_data.spd_data[0][0]) + |
| 418 | (!pei_data.spd_addresses[1] && !pei_data.spd_data[1][0]) * 2; |
| 419 | |
| 420 | pei_data.dimm_channel1_disabled = |
| 421 | (!pei_data.spd_addresses[2] && !pei_data.spd_data[2][0]) + |
| 422 | (!pei_data.spd_addresses[3] && !pei_data.spd_data[3][0]) * 2; |
| 423 | |
Patrick Rudolph | 59b4255 | 2019-05-08 12:44:15 +0200 | [diff] [blame] | 424 | /* Fix spd_data. MRC only uses spd_data[0] and ignores the other */ |
| 425 | for (size_t i = 1; i < ARRAY_SIZE(pei_data.spd_data); i++) { |
| 426 | if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) { |
| 427 | memcpy(pei_data.spd_data[0], pei_data.spd_data[i], |
| 428 | sizeof(pei_data.spd_data[0])); |
| 429 | } else if (pei_data.spd_data[i][0] && pei_data.spd_data[0][0]) { |
| 430 | if (memcmp(pei_data.spd_data[i], pei_data.spd_data[0], |
| 431 | sizeof(pei_data.spd_data[0])) != 0) |
| 432 | die("Onboard SPDs must match each other"); |
| 433 | } |
| 434 | } |
| 435 | |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 436 | disable_p2p(); |
| 437 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 438 | pei_data.boot_mode = s3resume ? 2 : 0; |
| 439 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 440 | sdram_initialize(&pei_data); |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 441 | |
| 442 | mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; |
| 443 | /* Sanity check mrc_var location by verifying a known field. */ |
| 444 | if (mrc_var->tx_byte == (uintptr_t)pei_data.tx_byte) { |
| 445 | printk(BIOS_DEBUG, "MRC_VAR pool occupied [%08x,%08x]\n", |
| 446 | mrc_var->pool_base, |
| 447 | mrc_var->pool_base + mrc_var->pool_used); |
| 448 | } else { |
| 449 | printk(BIOS_ERR, "Could not parse MRC_VAR data\n"); |
| 450 | hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); |
| 451 | } |
| 452 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 453 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 454 | if (!s3resume) |
| 455 | save_mrc_data(&pei_data); |
| 456 | |
| 457 | if (s3resume && !cbmem_was_initted) { |
| 458 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 459 | system_reset(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 460 | } |
| 461 | } |