Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Intel Corp. |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 5 | * Copyright (C) 2017-2019 Advanced Micro Devices, Inc. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <cpu/cpu.h> |
| 18 | #include <cpu/x86/mp.h> |
| 19 | #include <cpu/x86/mtrr.h> |
| 20 | #include <cpu/x86/msr.h> |
Kyösti Mälkki | b2a5f0b | 2019-08-04 19:54:32 +0300 | [diff] [blame] | 21 | #include <cpu/x86/smm.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 22 | #include <cpu/amd/msr.h> |
Kyösti Mälkki | e31ec29 | 2019-08-10 17:27:01 +0300 | [diff] [blame] | 23 | #include <cpu/amd/amd64_save_state.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci_ops.h> |
| 27 | #include <soc/pci_devs.h> |
| 28 | #include <soc/cpu.h> |
| 29 | #include <soc/northbridge.h> |
| 30 | #include <soc/smi.h> |
| 31 | #include <soc/iomap.h> |
| 32 | #include <console/console.h> |
| 33 | |
| 34 | /* |
| 35 | * MP and SMM loading initialization. |
| 36 | */ |
Kyösti Mälkki | 8699724 | 2019-08-06 01:44:58 +0300 | [diff] [blame^] | 37 | struct smm_relocation_params { |
| 38 | msr_t tseg_base; |
| 39 | msr_t tseg_mask; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 40 | }; |
| 41 | |
Kyösti Mälkki | 8699724 | 2019-08-06 01:44:58 +0300 | [diff] [blame^] | 42 | static struct smm_relocation_params smm_reloc_params; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * Do essential initialization tasks before APs can be fired up - |
| 46 | * |
| 47 | * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This |
| 48 | * creates the MTRR solution that the APs will use. Otherwise APs will try to |
| 49 | * apply the incomplete solution as the BSP is calculating it. |
| 50 | */ |
| 51 | static void pre_mp_init(void) |
| 52 | { |
| 53 | x86_setup_mtrrs_with_detect(); |
| 54 | x86_mtrr_check(); |
| 55 | } |
| 56 | |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 57 | int get_cpu_count(void) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 58 | { |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 59 | return 1 + (cpuid_ecx(0x80000008) & 0xff); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 60 | } |
| 61 | |
Kyösti Mälkki | 8699724 | 2019-08-06 01:44:58 +0300 | [diff] [blame^] | 62 | static void fill_in_relocation_params(struct smm_relocation_params *params) |
| 63 | { |
| 64 | uintptr_t tseg_base; |
| 65 | size_t tseg_size; |
| 66 | |
| 67 | smm_region(&tseg_base, &tseg_size); |
| 68 | |
| 69 | params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); |
| 70 | params->tseg_base.hi = 0; |
| 71 | params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); |
| 72 | params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); |
| 73 | |
| 74 | params->tseg_mask.lo |= SMM_TSEG_WB; |
| 75 | } |
| 76 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 77 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 78 | size_t *smm_save_state_size) |
| 79 | { |
Kyösti Mälkki | 8699724 | 2019-08-06 01:44:58 +0300 | [diff] [blame^] | 80 | printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 81 | |
Kyösti Mälkki | 8699724 | 2019-08-06 01:44:58 +0300 | [diff] [blame^] | 82 | fill_in_relocation_params(&smm_reloc_params); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 83 | |
Kyösti Mälkki | 8699724 | 2019-08-06 01:44:58 +0300 | [diff] [blame^] | 84 | smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 85 | *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); |
| 86 | } |
| 87 | |
| 88 | static void relocation_handler(int cpu, uintptr_t curr_smbase, |
| 89 | uintptr_t staggered_smbase) |
| 90 | { |
Kyösti Mälkki | 8699724 | 2019-08-06 01:44:58 +0300 | [diff] [blame^] | 91 | struct smm_relocation_params *relo_params = &smm_reloc_params; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 92 | amd64_smm_state_save_area_t *smm_state; |
| 93 | |
Kyösti Mälkki | 8699724 | 2019-08-06 01:44:58 +0300 | [diff] [blame^] | 94 | wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); |
| 95 | wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); |
| 96 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 97 | smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); |
| 98 | smm_state->smbase = staggered_smbase; |
| 99 | } |
| 100 | |
| 101 | static const struct mp_ops mp_ops = { |
| 102 | .pre_mp_init = pre_mp_init, |
| 103 | .get_cpu_count = get_cpu_count, |
| 104 | .get_smm_info = get_smm_info, |
| 105 | .relocation_handler = relocation_handler, |
| 106 | .post_mp_init = enable_smi_generation, |
| 107 | }; |
| 108 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 109 | void picasso_init_cpus(struct device *dev) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 110 | { |
| 111 | /* Clear for take-off */ |
| 112 | if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) |
| 113 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 114 | |
| 115 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
| 116 | mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
| 117 | |
| 118 | set_warm_reset_flag(); |
| 119 | } |
| 120 | |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 121 | static void model_17_init(struct device *dev) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 122 | { |
| 123 | check_mca(); |
| 124 | setup_lapic(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | static struct device_operations cpu_dev_ops = { |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 128 | .init = model_17_init, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 129 | }; |
| 130 | |
| 131 | static struct cpu_device_id cpu_table[] = { |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 132 | { X86_VENDOR_AMD, 0x810f81 }, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 133 | { 0, 0 }, |
| 134 | }; |
| 135 | |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 136 | static const struct cpu_driver model_17 __cpu_driver = { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 137 | .ops = &cpu_dev_ops, |
| 138 | .id_table = cpu_table, |
| 139 | }; |