Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Intel Corp. |
| 5 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <cpu/cpu.h> |
| 18 | #include <cpu/x86/mp.h> |
| 19 | #include <cpu/x86/mtrr.h> |
| 20 | #include <cpu/x86/msr.h> |
| 21 | #include <cpu/amd/msr.h> |
| 22 | #include <cpu/x86/lapic.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci_ops.h> |
| 25 | #include <soc/pci_devs.h> |
| 26 | #include <soc/cpu.h> |
| 27 | #include <soc/northbridge.h> |
| 28 | #include <soc/smi.h> |
| 29 | #include <soc/iomap.h> |
| 30 | #include <console/console.h> |
| 31 | |
| 32 | /* |
| 33 | * MP and SMM loading initialization. |
| 34 | */ |
| 35 | struct smm_relocation_attrs { |
| 36 | uint32_t smbase; |
| 37 | uint32_t tseg_base; |
| 38 | uint32_t tseg_mask; |
| 39 | }; |
| 40 | |
| 41 | static struct smm_relocation_attrs relo_attrs; |
| 42 | |
| 43 | /* |
| 44 | * Do essential initialization tasks before APs can be fired up - |
| 45 | * |
| 46 | * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This |
| 47 | * creates the MTRR solution that the APs will use. Otherwise APs will try to |
| 48 | * apply the incomplete solution as the BSP is calculating it. |
| 49 | */ |
| 50 | static void pre_mp_init(void) |
| 51 | { |
| 52 | x86_setup_mtrrs_with_detect(); |
| 53 | x86_mtrr_check(); |
| 54 | } |
| 55 | |
| 56 | static int get_cpu_count(void) |
| 57 | { |
| 58 | return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) |
| 59 | + 1; |
| 60 | } |
| 61 | |
| 62 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 63 | size_t *smm_save_state_size) |
| 64 | { |
| 65 | void *smm_base; |
| 66 | size_t smm_size; |
| 67 | void *handler_base; |
| 68 | size_t handler_size; |
| 69 | |
| 70 | /* Initialize global tracking state. */ |
| 71 | smm_region_info(&smm_base, &smm_size); |
| 72 | smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); |
| 73 | |
| 74 | relo_attrs.smbase = (uint32_t)smm_base; |
| 75 | relo_attrs.tseg_base = relo_attrs.smbase; |
| 76 | relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); |
| 77 | relo_attrs.tseg_mask |= SMM_TSEG_WB; |
| 78 | |
| 79 | *perm_smbase = (uintptr_t)handler_base; |
| 80 | *perm_smsize = handler_size; |
| 81 | *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); |
| 82 | } |
| 83 | |
| 84 | static void relocation_handler(int cpu, uintptr_t curr_smbase, |
| 85 | uintptr_t staggered_smbase) |
| 86 | { |
| 87 | msr_t tseg_base, tseg_mask; |
| 88 | amd64_smm_state_save_area_t *smm_state; |
| 89 | |
| 90 | tseg_base.lo = relo_attrs.tseg_base; |
| 91 | tseg_base.hi = 0; |
| 92 | wrmsr(SMM_ADDR_MSR, tseg_base); |
| 93 | tseg_mask.lo = relo_attrs.tseg_mask; |
| 94 | tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); |
| 95 | wrmsr(SMM_MASK_MSR, tseg_mask); |
| 96 | smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); |
| 97 | smm_state->smbase = staggered_smbase; |
| 98 | } |
| 99 | |
| 100 | static const struct mp_ops mp_ops = { |
| 101 | .pre_mp_init = pre_mp_init, |
| 102 | .get_cpu_count = get_cpu_count, |
| 103 | .get_smm_info = get_smm_info, |
| 104 | .relocation_handler = relocation_handler, |
| 105 | .post_mp_init = enable_smi_generation, |
| 106 | }; |
| 107 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame^] | 108 | void picasso_init_cpus(struct device *dev) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 109 | { |
| 110 | /* Clear for take-off */ |
| 111 | if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) |
| 112 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 113 | |
| 114 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
| 115 | mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
| 116 | |
| 117 | set_warm_reset_flag(); |
| 118 | } |
| 119 | |
| 120 | static void model_15_init(struct device *dev) |
| 121 | { |
| 122 | check_mca(); |
| 123 | setup_lapic(); |
| 124 | |
| 125 | /* |
| 126 | * Per AMD, sync an undocumented MSR with the PSP base address. |
| 127 | * Experiments showed that if you write to the MSR after it has |
| 128 | * been previously programmed, it causes a general protection fault. |
| 129 | * Also, the MSR survives warm reset and S3 cycles, so we need to |
| 130 | * test if it was previously written before writing to it. |
| 131 | */ |
| 132 | msr_t psp_msr; |
| 133 | uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ |
| 134 | psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); |
| 135 | psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 136 | psp_msr = rdmsr(0xc00110a2); |
| 137 | if (psp_msr.lo == 0) { |
| 138 | psp_msr.lo = psp_bar; |
| 139 | wrmsr(0xc00110a2, psp_msr); |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | static struct device_operations cpu_dev_ops = { |
| 144 | .init = model_15_init, |
| 145 | }; |
| 146 | |
| 147 | static struct cpu_device_id cpu_table[] = { |
| 148 | { X86_VENDOR_AMD, 0x670f00 }, |
| 149 | { 0, 0 }, |
| 150 | }; |
| 151 | |
| 152 | static const struct cpu_driver model_15 __cpu_driver = { |
| 153 | .ops = &cpu_dev_ops, |
| 154 | .id_table = cpu_table, |
| 155 | }; |