Patrick Georgi | 11f0079 | 2020-03-04 15:10:45 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 2 | |
Kyösti Mälkki | ed318f2 | 2019-01-11 21:07:36 +0200 | [diff] [blame] | 3 | /* CACHE_ROM_SIZE defined here. */ |
| 4 | #include <cpu/x86/mtrr.h> |
Arthur Heymans | 28de28d | 2022-05-15 21:46:44 +0200 | [diff] [blame] | 5 | #include <memlayout.h> |
Kyösti Mälkki | ed318f2 | 2019-01-11 21:07:36 +0200 | [diff] [blame] | 6 | |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 7 | /* This file is included inside a SECTIONS block */ |
| 8 | . = CONFIG_DCACHE_RAM_BASE; |
| 9 | .car.data . (NOLOAD) : { |
Andrey Petrov | dd56de9 | 2016-02-25 17:22:17 -0800 | [diff] [blame] | 10 | _car_region_start = . ; |
Arthur Heymans | 7a5c369 | 2021-01-04 12:49:39 +0100 | [diff] [blame] | 11 | . += CONFIG_FSP_M_RC_HEAP_SIZE; |
Arthur Heymans | 0201d98 | 2024-02-18 11:45:30 +0100 | [diff] [blame] | 12 | #if CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND) |
| 13 | REGION(fspm_heap, ., CONFIG_FSP_TEMP_RAM_SIZE, 16) |
| 14 | #endif |
| 15 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 16 | #if CONFIG(PAGING_IN_CACHE_AS_RAM) |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 17 | /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB |
| 18 | * aligned when using this option. */ |
Julius Werner | 82d16b1 | 2020-12-30 15:51:10 -0800 | [diff] [blame] | 19 | REGION(pagetables, ., 4K * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4K) |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 20 | #endif |
Frans Hendriks | d42154a | 2020-11-13 11:57:23 +0100 | [diff] [blame] | 21 | #if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) |
Joel Kitching | d6f71d0 | 2019-02-21 12:37:55 +0800 | [diff] [blame] | 22 | /* Vboot work buffer only needs to be available when verified boot |
| 23 | * starts in bootblock. */ |
Jeremy Compostella | 0c8e541 | 2023-11-27 15:05:29 -0800 | [diff] [blame] | 24 | VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) |
Aaron Durbin | 75c51d9 | 2015-09-29 16:31:20 -0500 | [diff] [blame] | 25 | #endif |
Bill XIE | c79e96b | 2019-08-22 20:28:36 +0800 | [diff] [blame] | 26 | #if CONFIG(TPM_MEASURED_BOOT) |
Sergii Dmytruk | 2710df7 | 2022-11-10 00:40:51 +0200 | [diff] [blame] | 27 | /* Vboot measured boot TPM log measurements. |
Frans Hendriks | d42154a | 2020-11-13 11:57:23 +0100 | [diff] [blame] | 28 | * Needs to be transferred until CBMEM is available */ |
Sergii Dmytruk | 2710df7 | 2022-11-10 00:40:51 +0200 | [diff] [blame] | 29 | TPM_LOG(., 2K) |
Arthur Heymans | 3c61304 | 2019-04-21 23:59:47 +0200 | [diff] [blame] | 30 | #endif |
Andrey Petrov | ee9e4ae | 2016-02-08 17:17:05 -0800 | [diff] [blame] | 31 | /* Stack for CAR stages. Since it persists across all stages that |
| 32 | * use CAR it can be reused. The chipset/SoC is expected to provide |
| 33 | * the stack size. */ |
Julius Werner | 82d16b1 | 2020-12-30 15:51:10 -0800 | [diff] [blame] | 34 | REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 4) |
Aaron Durbin | dd6fa93 | 2015-09-24 12:18:07 -0500 | [diff] [blame] | 35 | /* The pre-ram cbmem console as well as the timestamp region are fixed |
Arthur Heymans | 4cc9b6c | 2018-12-28 17:53:36 +0100 | [diff] [blame] | 36 | * in size. Therefore place them above the car global section so that |
Frans Hendriks | d42154a | 2020-11-13 11:57:23 +0100 | [diff] [blame] | 37 | * multiple stages (romstage and verstage) have a consistent |
| 38 | * link address of these shared objects. */ |
Kyösti Mälkki | 513a1a8 | 2018-06-03 12:29:50 +0300 | [diff] [blame] | 39 | PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 40 | #if CONFIG(PAGING_IN_CACHE_AS_RAM) |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 41 | . = ALIGN(32); |
| 42 | /* Page directory pointer table resides here. There are 4 8-byte entries |
| 43 | * totalling 32 bytes that need to be 32-byte aligned. The reason the |
| 44 | * pdpt are not colocated with the rest of the page tables is to reduce |
| 45 | * fragmentation of the CAR space that persists across stages. */ |
Julius Werner | 82d16b1 | 2020-12-30 15:51:10 -0800 | [diff] [blame] | 46 | REGION(pdpt, ., 32, 32) |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 47 | #endif |
Kyösti Mälkki | 3dd23a5 | 2019-08-22 15:06:50 +0300 | [diff] [blame] | 48 | |
Furquan Shaikh | 549080b | 2018-05-17 23:30:28 -0700 | [diff] [blame] | 49 | TIMESTAMP(., 0x200) |
Julius Werner | 7fc9286 | 2019-11-18 13:01:06 -0800 | [diff] [blame] | 50 | |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 51 | #if !CONFIG(NO_CBFS_MCACHE) |
| 52 | CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) |
| 53 | #endif |
Julius Werner | 7fc9286 | 2019-11-18 13:01:06 -0800 | [diff] [blame] | 54 | #if !CONFIG(NO_FMAP_CACHE) |
Julius Werner | cefe89e | 2019-11-06 19:29:44 -0800 | [diff] [blame] | 55 | FMAP_CACHE(., FMAP_SIZE) |
Julius Werner | 7fc9286 | 2019-11-18 13:01:06 -0800 | [diff] [blame] | 56 | #endif |
Kyösti Mälkki | 3dd23a5 | 2019-08-22 15:06:50 +0300 | [diff] [blame] | 57 | |
Jeremy Compostella | 052fb7c | 2023-08-18 14:25:22 -0700 | [diff] [blame] | 58 | . = ALIGN(CONFIG_CBFS_CACHE_ALIGN); |
| 59 | CBFS_CACHE(., CONFIG_PRERAM_CBFS_CACHE_SIZE) |
| 60 | |
Kyösti Mälkki | f88208e | 2019-01-31 08:29:32 +0200 | [diff] [blame] | 61 | /* Reserve sizeof(struct ehci_dbg_info). */ |
Julius Werner | 82d16b1 | 2020-12-30 15:51:10 -0800 | [diff] [blame] | 62 | REGION(car_ehci_dbg_info, ., 80, 1) |
Kyösti Mälkki | 3dd23a5 | 2019-08-22 15:06:50 +0300 | [diff] [blame] | 63 | |
Kyösti Mälkki | 910490f | 2019-08-22 12:56:22 +0300 | [diff] [blame] | 64 | /* _bss and _ebss provide symbols to per-stage |
Aaron Durbin | dd6fa93 | 2015-09-24 12:18:07 -0500 | [diff] [blame] | 65 | * variables that are not shared like the timestamp and the pre-ram |
| 66 | * cbmem console. This is useful for clearing this area on a per-stage |
Arthur Heymans | fdb8b13 | 2019-11-28 14:00:01 +0100 | [diff] [blame] | 67 | * basis when more than one stage uses cache-as-ram. */ |
Kyösti Mälkki | 910490f | 2019-08-22 12:56:22 +0300 | [diff] [blame] | 68 | |
Jeremy Compostella | b7832de | 2023-08-30 15:42:09 -0700 | [diff] [blame] | 69 | #if ENV_SEPARATE_DATA_AND_BSS |
Kyösti Mälkki | 910490f | 2019-08-22 12:56:22 +0300 | [diff] [blame] | 70 | . = ALIGN(ARCH_POINTER_ALIGN_SIZE); |
| 71 | _bss = .; |
Kyösti Mälkki | a165c07 | 2019-08-22 09:44:44 +0300 | [diff] [blame] | 72 | /* Allow global uninitialized variables for stages without CAR teardown. */ |
Aaron Durbin | 76ab2b7 | 2018-10-30 12:15:10 -0600 | [diff] [blame] | 73 | *(.bss) |
| 74 | *(.bss.*) |
Arthur Heymans | 8406fb4 | 2024-04-05 09:00:06 +0200 | [diff] [blame^] | 75 | *(.lbss) |
| 76 | *(.lbss.*) |
Aaron Durbin | 76ab2b7 | 2018-10-30 12:15:10 -0600 | [diff] [blame] | 77 | *(.sbss) |
| 78 | *(.sbss.*) |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 79 | . = ALIGN(ARCH_POINTER_ALIGN_SIZE); |
Kyösti Mälkki | 910490f | 2019-08-22 12:56:22 +0300 | [diff] [blame] | 80 | _ebss = .; |
Julius Werner | 82d16b1 | 2020-12-30 15:51:10 -0800 | [diff] [blame] | 81 | RECORD_SIZE(bss) |
Arthur Heymans | 9efb0c0 | 2020-11-30 14:03:51 +0100 | [diff] [blame] | 82 | #endif |
Andrey Petrov | dd56de9 | 2016-02-25 17:22:17 -0800 | [diff] [blame] | 83 | |
Arthur Heymans | a2bc254 | 2021-05-29 08:10:49 +0200 | [diff] [blame] | 84 | #if ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) |
Harshit Sharma | a6ebe08 | 2020-07-20 00:21:05 -0700 | [diff] [blame] | 85 | _shadow_size = (_ebss - _car_region_start) >> 3; |
| 86 | REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE) |
| 87 | #endif |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 88 | } |
Arthur Heymans | 7a5c369 | 2021-01-04 12:49:39 +0100 | [diff] [blame] | 89 | |
Jeremy Compostella | b7832de | 2023-08-30 15:42:09 -0700 | [diff] [blame] | 90 | #if ENV_SEPARATE_DATA_AND_BSS |
| 91 | /* This symbol defines the load address of the Cache-As-RAM .data |
| 92 | * section. It should be right at the end of the .text section (_etext) |
| 93 | * and ARCH_POINTER_ALIGN_SIZE aligned. */ |
| 94 | _data_load = _etext; |
| 95 | |
| 96 | _bogus = ASSERT(_etext == ALIGN(_etext, ARCH_POINTER_ALIGN_SIZE), "Cache-As-RAM load address is improperly defined."); |
| 97 | |
| 98 | .data ALIGN(ARCH_POINTER_ALIGN_SIZE) : AT (_data_load) { |
| 99 | _data = .; |
| 100 | *(.data); |
| 101 | *(.data.*); |
Arthur Heymans | 8406fb4 | 2024-04-05 09:00:06 +0200 | [diff] [blame^] | 102 | *(.ldata); |
| 103 | *(.ldata.*); |
Jeremy Compostella | b7832de | 2023-08-30 15:42:09 -0700 | [diff] [blame] | 104 | *(.sdata); |
| 105 | *(.sdata.*); |
| 106 | . = ALIGN(ARCH_POINTER_ALIGN_SIZE); |
| 107 | _edata = .; |
| 108 | RECORD_SIZE(data) |
| 109 | } : data_segment |
| 110 | #endif |
| 111 | |
| 112 | _car_unallocated_start = .; |
| 113 | _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start) |
| 114 | - CONFIG_FSP_T_RESERVED_SIZE; |
| 115 | |
Arthur Heymans | 7a5c369 | 2021-01-04 12:49:39 +0100 | [diff] [blame] | 116 | . = _car_region_start; |
| 117 | .car.fspm_rc_heap . (NOLOAD) : { |
Arthur Heymans | 0201d98 | 2024-02-18 11:45:30 +0100 | [diff] [blame] | 118 | . += CONFIG_FSP_M_RC_HEAP_SIZE; |
Arthur Heymans | 7a5c369 | 2021-01-04 12:49:39 +0100 | [diff] [blame] | 119 | } |
| 120 | |
Kyösti Mälkki | ed318f2 | 2019-01-11 21:07:36 +0200 | [diff] [blame] | 121 | . = _car_region_end; |
| 122 | .car.mrc_var . (NOLOAD) : { |
| 123 | . += CONFIG_DCACHE_RAM_MRC_VAR_SIZE; |
| 124 | } |
Arthur Heymans | 9789689 | 2021-01-04 12:22:57 +0100 | [diff] [blame] | 125 | .car.fspt_reserved . (NOLOAD) : { |
| 126 | . += CONFIG_FSP_T_RESERVED_SIZE; |
| 127 | } |
| 128 | |
Kyösti Mälkki | ed318f2 | 2019-01-11 21:07:36 +0200 | [diff] [blame] | 129 | #if ENV_BOOTBLOCK |
| 130 | _car_mtrr_end = .; |
| 131 | _car_mtrr_start = _car_region_start; |
| 132 | |
| 133 | _car_mtrr_size = _car_mtrr_end - _car_mtrr_start; |
| 134 | _car_mtrr_sz_log2 = 1 << LOG2CEIL(_car_mtrr_size); |
| 135 | _car_mtrr_mask = ~(MAX(4096, _car_mtrr_sz_log2) - 1); |
| 136 | |
| 137 | #if !CONFIG(NO_XIP_EARLY_STAGES) |
| 138 | _xip_program_sz_log2 = 1 << LOG2CEIL(_ebootblock - _bootblock); |
| 139 | _xip_mtrr_mask = ~(MAX(4096, _xip_program_sz_log2) - 1); |
| 140 | #endif |
| 141 | |
| 142 | _rom_mtrr_mask = ~(CACHE_ROM_SIZE - 1); |
| 143 | _rom_mtrr_base = _rom_mtrr_mask; |
| 144 | #endif |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 145 | |
Jeremy Compostella | b7832de | 2023-08-30 15:42:09 -0700 | [diff] [blame] | 146 | #if ENV_SEPARATE_DATA_AND_BSS |
| 147 | _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + SIZEOF(.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); |
| 148 | #else |
Aaron Durbin | dd6fa93 | 2015-09-24 12:18:07 -0500 | [diff] [blame] | 149 | _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); |
Jeremy Compostella | b7832de | 2023-08-30 15:42:09 -0700 | [diff] [blame] | 150 | #endif |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 151 | #if CONFIG(PAGING_IN_CACHE_AS_RAM) |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 152 | _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); |
| 153 | #endif |
Patrick Rudolph | d72d52a | 2018-11-12 19:26:54 +0100 | [diff] [blame] | 154 | _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); |
Arthur Heymans | a2bc254 | 2021-05-29 08:10:49 +0200 | [diff] [blame] | 155 | #if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_SEPARATE_ROMSTAGE || ENV_SEPARATE_VERSTAGE) |
Arthur Heymans | c27628e | 2019-11-05 00:46:01 +0100 | [diff] [blame] | 156 | _bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !"); |
| 157 | _bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!"); |
| 158 | #endif |