Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2008-2010 coresystems GmbH |
| 6 | * Copyright 2015 Google Inc |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | /* This file is included inside a SECTIONS block */ |
| 19 | . = CONFIG_DCACHE_RAM_BASE; |
| 20 | .car.data . (NOLOAD) : { |
Andrey Petrov | dd56de9 | 2016-02-25 17:22:17 -0800 | [diff] [blame] | 21 | _car_region_start = . ; |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 22 | #if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) |
| 23 | /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB |
| 24 | * aligned when using this option. */ |
| 25 | _pagetables = . ; |
| 26 | . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; |
| 27 | _epagetables = . ; |
| 28 | #endif |
Aaron Durbin | 75c51d9 | 2015-09-29 16:31:20 -0500 | [diff] [blame] | 29 | /* Vboot work buffer is completely volatile outside of verstage and |
| 30 | * romstage. Appropriate code needs to handle the transition. */ |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 31 | #if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) |
Aaron Durbin | 75c51d9 | 2015-09-29 16:31:20 -0500 | [diff] [blame] | 32 | VBOOT2_WORK(., 16K) |
| 33 | #endif |
Andrey Petrov | ee9e4ae | 2016-02-08 17:17:05 -0800 | [diff] [blame] | 34 | /* Stack for CAR stages. Since it persists across all stages that |
| 35 | * use CAR it can be reused. The chipset/SoC is expected to provide |
| 36 | * the stack size. */ |
| 37 | #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) |
| 38 | _car_stack_start = .; |
| 39 | . += CONFIG_DCACHE_BSP_STACK_SIZE; |
| 40 | _car_stack_end = .; |
| 41 | #endif |
Aaron Durbin | dd6fa93 | 2015-09-24 12:18:07 -0500 | [diff] [blame] | 42 | /* The pre-ram cbmem console as well as the timestamp region are fixed |
| 43 | * in size. Therefore place them at the beginning .car.data section |
| 44 | * so that multiple stages (romstage and verstage) have a consistent |
| 45 | * link address of these shared objects. */ |
Naresh G Solanki | 04bb480 | 2016-12-13 21:16:46 +0530 | [diff] [blame] | 46 | PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)) |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 47 | #if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) |
| 48 | . = ALIGN(32); |
| 49 | /* Page directory pointer table resides here. There are 4 8-byte entries |
| 50 | * totalling 32 bytes that need to be 32-byte aligned. The reason the |
| 51 | * pdpt are not colocated with the rest of the page tables is to reduce |
| 52 | * fragmentation of the CAR space that persists across stages. */ |
| 53 | _pdpt = .; |
| 54 | . += 32; |
| 55 | _epdpt = .; |
| 56 | #endif |
Andrey Petrov | dd56de9 | 2016-02-25 17:22:17 -0800 | [diff] [blame] | 57 | _car_relocatable_data_start = .; |
Aaron Durbin | dd6fa93 | 2015-09-24 12:18:07 -0500 | [diff] [blame] | 58 | /* The timestamp implementation relies on this storage to be around |
| 59 | * after migration. One of the fields indicates not to use it as the |
| 60 | * backing store once cbmem comes online. Therefore, this data needs |
Andrey Petrov | dd56de9 | 2016-02-25 17:22:17 -0800 | [diff] [blame] | 61 | * to reside in the migrated area (between _car_relocatable_data_start |
| 62 | * and _car_relocatable_data_end). */ |
Furquan Shaikh | 549080b | 2018-05-17 23:30:28 -0700 | [diff] [blame] | 63 | TIMESTAMP(., 0x200) |
Lee Leahy | 48dbc66 | 2017-05-08 16:56:03 -0700 | [diff] [blame] | 64 | #if IS_ENABLED(CONFIG_COMMONLIB_STORAGE) |
Lee Leahy | 43d0d0d | 2017-04-14 09:42:59 -0700 | [diff] [blame] | 65 | _car_drivers_storage_start = .; |
| 66 | . += 256; |
| 67 | _car_drivers_storage_end = .; |
| 68 | #endif |
Aaron Durbin | dd6fa93 | 2015-09-24 12:18:07 -0500 | [diff] [blame] | 69 | /* _car_global_start and _car_global_end provide symbols to per-stage |
| 70 | * variables that are not shared like the timestamp and the pre-ram |
| 71 | * cbmem console. This is useful for clearing this area on a per-stage |
| 72 | * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ |
| 73 | _car_global_start = .; |
Aaron Durbin | 76ab2b7 | 2018-10-30 12:15:10 -0600 | [diff] [blame^] | 74 | #if IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) |
| 75 | /* Allow global unitialized variables when CAR_GLOBALs are not used. */ |
| 76 | *(.bss) |
| 77 | *(.bss.*) |
| 78 | *(.sbss) |
| 79 | *(.sbss.*) |
| 80 | #else |
| 81 | /* .car.global_data objects only around when |
| 82 | * !CONFIG_NO_CAR_GLOBAL_MIGRATION is employed. */ |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 83 | *(.car.global_data); |
Aaron Durbin | 76ab2b7 | 2018-10-30 12:15:10 -0600 | [diff] [blame^] | 84 | #endif |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 85 | . = ALIGN(ARCH_POINTER_ALIGN_SIZE); |
Aaron Durbin | dd6fa93 | 2015-09-24 12:18:07 -0500 | [diff] [blame] | 86 | _car_global_end = .; |
Andrey Petrov | dd56de9 | 2016-02-25 17:22:17 -0800 | [diff] [blame] | 87 | _car_relocatable_data_end = .; |
| 88 | |
| 89 | _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | /* Global variables are not allowed in romstage |
| 93 | * This section is checked during stage creation to ensure |
| 94 | * that there are no global variables present |
| 95 | */ |
| 96 | |
| 97 | . = 0xffffff00; |
| 98 | .illegal_globals . : { |
Nico Huber | 98fc426 | 2016-01-23 01:24:33 +0100 | [diff] [blame] | 99 | *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) |
| 100 | *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) |
Aaron Durbin | 76ab2b7 | 2018-10-30 12:15:10 -0600 | [diff] [blame^] | 101 | #if !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 102 | *(.bss) |
| 103 | *(.bss.*) |
| 104 | *(.sbss) |
| 105 | *(.sbss.*) |
Aaron Durbin | 76ab2b7 | 2018-10-30 12:15:10 -0600 | [diff] [blame^] | 106 | #else |
| 107 | /* In case something sneaks through when it shouldn't. */ |
| 108 | *(.car.global_data); |
| 109 | #endif |
Aaron Durbin | 956c4f2 | 2015-09-05 13:31:14 -0500 | [diff] [blame] | 110 | } |
| 111 | |
Aaron Durbin | dd6fa93 | 2015-09-24 12:18:07 -0500 | [diff] [blame] | 112 | _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 113 | #if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) |
| 114 | _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); |
| 115 | #endif |