Martin Roth | 7d86f34 | 2024-02-16 11:04:02 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Subrata Banik | 76806c3 | 2022-01-03 17:33:35 +0000 | [diff] [blame] | 3 | config DISABLE_HECI1_AT_PRE_BOOT |
| 4 | bool "Disable HECI1 at the end of boot" |
| 5 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 6 | default n |
| 7 | help |
| 8 | This config decides the state of HECI1(CSE) device at the end of boot. |
| 9 | Mainboard users to select this config to make HECI1 `function disable` |
| 10 | prior to handing off to payload. |
| 11 | |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 12 | config MAX_HECI_DEVICES |
| 13 | int |
| 14 | default 6 |
| 15 | |
| 16 | config SOC_INTEL_COMMON_BLOCK_CSE |
| 17 | bool |
| 18 | default n |
| 19 | help |
| 20 | Driver for communication with Converged Security Engine (CSE) |
| 21 | over Host Embedded Controller Interface (HECI) |
| 22 | |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 23 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI |
Subrata Banik | 7e89984 | 2018-05-17 18:28:26 +0530 | [diff] [blame] | 24 | bool |
| 25 | default y if HECI_DISABLE_USING_SMM |
| 26 | select SOC_INTEL_COMMON_BLOCK_P2SB |
| 27 | help |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 28 | Use this config to allow common CSE block to make HECI1 function disable |
| 29 | in the SMM mode. From CNL PCH onwards,`HECI1` disabling can only be done |
| 30 | using the non-posted sideband write after FSP-S sets the postboot_sai |
| 31 | attribute. |
| 32 | |
| 33 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
| 34 | bool |
| 35 | default n |
| 36 | select SOC_INTEL_COMMON_BLOCK_PMC |
| 37 | help |
| 38 | Use this config to allow common CSE block to make HECI1 function disable |
| 39 | using PMC IPC command `0xA9`. From TGL PCH onwards, disabling heci1 |
| 40 | device using PMC IPC doesn't required to run the operation in SMM. |
| 41 | |
| 42 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR |
| 43 | bool |
| 44 | default n |
| 45 | select SOC_INTEL_COMMON_BLOCK_PCR |
| 46 | help |
| 47 | Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) |
| 48 | to make `HECI1` device disable using private configuration register (PCR) write. |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 49 | |
Subrata Banik | 2172a63 | 2023-06-22 01:00:06 +0530 | [diff] [blame] | 50 | config SOC_INTEL_STORE_CSE_FW_VERSION |
| 51 | bool |
Subrata Banik | c8a0417 | 2023-08-13 13:17:22 +0000 | [diff] [blame] | 52 | default y |
Subrata Banik | 2172a63 | 2023-06-22 01:00:06 +0530 | [diff] [blame] | 53 | depends on SOC_INTEL_CSE_LITE_SKU |
| 54 | help |
| 55 | This configuration option stores CSE RW FW version in CBMEM area. |
| 56 | This information can be used to identify if the CSE firmware update is successful |
| 57 | by comparing the currently running CSE RW firmware version against CSE version |
| 58 | belongs to the CONFIG_SOC_INTEL_CSE_RW_VERSION (decided statically while |
| 59 | building the AP FW image). |
| 60 | |
| 61 | The way to retrieve the CSE firmware version is by sending the HECI command to |
| 62 | read the CSE Boot Partition (BP) info. The cost of sending HECI command to read |
| 63 | the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence, |
| 64 | ensure this feature is platform specific and only enabled for the platform |
| 65 | that would like to store the CSE version into the CBMEM. |
| 66 | |
Dinesh Gehlot | 91da19c | 2023-05-07 13:47:49 +0000 | [diff] [blame] | 67 | config SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET |
| 68 | int |
| 69 | default 68 |
| 70 | depends on SOC_INTEL_CSE_LITE_SKU |
| 71 | help |
| 72 | This configuration option stores the starting offset of cse fw partition versions in |
| 73 | CMOS memory. The offset should be byte aligned and must leave enough memory to store |
| 74 | required firmware partition versions. |
| 75 | |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 76 | config SOC_INTEL_STORE_ISH_FW_VERSION |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 77 | bool |
| 78 | default n |
| 79 | depends on DRIVERS_INTEL_ISH |
| 80 | help |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 81 | This configuration option stores ISH version in CBMEM area. |
| 82 | This information can be used to identify the currently running ISH firmware |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 83 | version. |
| 84 | |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 85 | ISH BUP is sitting inside the CSE firmware partition. The way to retrieve the |
| 86 | ISH version is by sending the HECI command to read the CSE FPT. The cost of sending |
| 87 | HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to |
| 88 | read the CSE RW version on every cold reset (to cover the CSE update scenarios) |
| 89 | and store into CBMEM to avoid the cost of resending the HECI command in all |
| 90 | consecutive warm boots. |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 91 | |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 92 | Later boot stages can just read the CBMEM ID to retrieve the ISH version. |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 93 | |
| 94 | Additionally, ensure this feature is platform specific hence, only enabled |
| 95 | for the platform that would like to store the ISH version into the CBMEM and |
| 96 | parse to perform some additional work. |
| 97 | |
MAULIK V VAGHELA | 61b8f89 | 2021-12-17 17:55:22 +0530 | [diff] [blame] | 98 | config SOC_INTEL_CSE_SEND_EOP_EARLY |
Michał Kopeć | 9c4ae91 | 2022-10-29 18:00:18 +0200 | [diff] [blame] | 99 | bool "CSE send EOP early" |
MAULIK V VAGHELA | 61b8f89 | 2021-12-17 17:55:22 +0530 | [diff] [blame] | 100 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 101 | help |
| 102 | Use this config to send End Of Post (EOP) earlier through SoC code in order to |
| 103 | reduce time required to send EOP and getting CSE response. |
| 104 | In later stages, CSE might be busy and might require more time to process EOP command. |
| 105 | SoC can use this Kconfig to send EOP earlier by itself. |
| 106 | |
Subrata Banik | bed82b0 | 2022-11-24 21:02:00 +0530 | [diff] [blame] | 107 | config SOC_INTEL_CSE_SEND_EOP_LATE |
| 108 | bool |
| 109 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 110 | help |
| 111 | Use this config to send End Of Post (EOP) late (even after CSE `final` operation) |
| 112 | using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code |
| 113 | in order to reduce time required to send EOP and getting CSE response. |
| 114 | It has been observed that CSE might be busy and might require more time to |
| 115 | process the EOP command. |
| 116 | SoC can use this Kconfig to send EOP later by itself. |
| 117 | Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this |
| 118 | config is applicable for those platforms. |
| 119 | |
Jeremy Compostella | 1d79188 | 2023-03-13 13:59:08 -0700 | [diff] [blame] | 120 | config SOC_INTEL_CSE_SEND_EOP_ASYNC |
| 121 | bool |
| 122 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 123 | depends on !SOC_INTEL_CSE_SEND_EOP_LATE |
| 124 | depends on !SOC_INTEL_CSE_SEND_EOP_EARLY |
| 125 | help |
| 126 | Use this config to handle End Of Post (EOP) completion |
| 127 | asynchronously. The EOP command is sent first and the result |
| 128 | is checked later leaving time to CSE to complete the |
| 129 | operation while coreboot perform other activities. |
| 130 | Performing EOP asynchronously reduces the time spent |
| 131 | actively waiting for command completion which can have a |
| 132 | significant impact on boot time. |
| 133 | |
| 134 | Using this asynchronous approach comes with the limitation |
| 135 | that no HECI command should be sent between the time the EOP |
| 136 | request is posted (at CSE .final device operation) and the |
| 137 | time coreboot check for its completion (BS_PAYLOAD_LOAD). |
| 138 | |
Kapil Porwal | e1b5996 | 2023-04-26 00:33:53 +0530 | [diff] [blame] | 139 | config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD |
| 140 | bool |
| 141 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 142 | depends on !SOC_INTEL_CSE_SEND_EOP_LATE |
| 143 | depends on !SOC_INTEL_CSE_SEND_EOP_EARLY |
| 144 | depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC |
| 145 | depends on !DISABLE_HECI1_AT_PRE_BOOT |
| 146 | help |
| 147 | Use this config to specify that the payload will send the End Of Post (EOP) instead |
| 148 | of coreboot. |
| 149 | |
| 150 | In this case, the HECI interface needs to stay visible and the payload must support |
| 151 | sending commands to CSE. |
| 152 | |
Kapil Porwal | 83cd6f9 | 2024-05-26 16:23:17 +0000 | [diff] [blame^] | 153 | config SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD |
| 154 | bool |
| 155 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 156 | help |
| 157 | Use this config to specify that the payload will update the CSE RW partition instead |
| 158 | of coreboot. |
| 159 | |
| 160 | In this case, CSE shall not switch to RW partition and the payload must support |
| 161 | CSE RW update. |
| 162 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 163 | config SOC_INTEL_CSE_LITE_SKU |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 164 | bool |
| 165 | default n |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 166 | help |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 167 | Enables CSE Lite SKU |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 168 | |
Krishna Prasad Bhat | 9ab161d | 2023-07-18 14:25:37 +0530 | [diff] [blame] | 169 | config SOC_INTEL_CSE_LITE_PSR |
| 170 | bool |
| 171 | default n |
| 172 | depends on SOC_INTEL_CSE_LITE_SKU |
Krishna Prasad Bhat | d2bc30f | 2023-09-22 00:28:50 +0530 | [diff] [blame] | 173 | select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE |
Krishna Prasad Bhat | 9ab161d | 2023-07-18 14:25:37 +0530 | [diff] [blame] | 174 | help |
| 175 | Select this config if Platform Service Record(PSR) is supported by the platform. This |
| 176 | config is applicable only for Lite SKU, where PSR data backup is required prior to a |
Krishna Prasad Bhat | d2bc30f | 2023-09-22 00:28:50 +0530 | [diff] [blame] | 177 | CSE firmware downgrade during which CSE data is cleared. PSR services in CSE FW is |
| 178 | enabled only post DRAM init and the command to backup PSR data is also supported only |
| 179 | post DRAM init. Hence platform that selects PSR would need to perform CSE firmware sync |
| 180 | in ramstage. |
Krishna Prasad Bhat | 9ab161d | 2023-07-18 14:25:37 +0530 | [diff] [blame] | 181 | |
Johnny Lin | a3e68c9 | 2022-08-09 15:36:30 +0800 | [diff] [blame] | 182 | config SOC_INTEL_CSE_SERVER_SKU |
| 183 | bool |
| 184 | default n |
| 185 | help |
| 186 | Enables CSE Server SKU |
| 187 | |
V Sowmya | f990552 | 2020-11-12 20:19:04 +0530 | [diff] [blame] | 188 | config SOC_INTEL_CSE_RW_UPDATE |
| 189 | bool "Enable the CSE RW Update Feature" |
| 190 | default n |
| 191 | depends on SOC_INTEL_CSE_LITE_SKU |
| 192 | help |
| 193 | This config will enable CSE RW firmware update feature and also will be used ensure |
| 194 | all the required configs are provided by mainboard. |
| 195 | |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 196 | config SOC_INTEL_CSE_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 197 | string "Name of CSE Region in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 198 | default "SI_ME" |
| 199 | help |
| 200 | Name of CSE region in FMAP |
| 201 | |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 202 | config SOC_INTEL_CSE_RW_A_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 203 | string "Location of CSE RW A in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 204 | default "ME_RW_A" |
| 205 | help |
| 206 | Name of CSE RW A region in FMAP |
| 207 | |
| 208 | config SOC_INTEL_CSE_RW_B_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 209 | string "Location of CSE RW B in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 210 | default "ME_RW_B" |
| 211 | help |
| 212 | Name of CSE RW B region in FMAP |
| 213 | |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 214 | config SOC_INTEL_CSE_RW_CBFS_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 215 | string "CBFS entry name for CSE RW blob" if SOC_INTEL_CSE_RW_UPDATE |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 216 | default "me_rw" |
| 217 | help |
| 218 | CBFS entry name for Intel CSE CBFS RW blob |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 219 | |
Furquan Shaikh | d2da870 | 2021-10-07 00:08:59 -0700 | [diff] [blame] | 220 | config SOC_INTEL_CSE_RW_HASH_CBFS_NAME |
| 221 | string "CBFS name for CSE RW hash file" if SOC_INTEL_CSE_RW_UPDATE |
| 222 | default "me_rw.hash" |
V Sowmya | 338b83c | 2020-11-11 07:04:13 +0530 | [diff] [blame] | 223 | help |
Furquan Shaikh | d2da870 | 2021-10-07 00:08:59 -0700 | [diff] [blame] | 224 | CBFS name for Intel CSE CBFS RW hash file |
| 225 | |
| 226 | config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME |
| 227 | string "CBFS name for CSE RW version file" if SOC_INTEL_CSE_RW_UPDATE |
| 228 | default "me_rw.version" |
| 229 | help |
| 230 | CBFS name for Intel CSE CBFS RW version file |
V Sowmya | 338b83c | 2020-11-11 07:04:13 +0530 | [diff] [blame] | 231 | |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 232 | config SOC_INTEL_CSE_RW_FILE |
Furquan Shaikh | 3f0d643 | 2021-10-09 00:08:56 -0700 | [diff] [blame] | 233 | string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE && !STITCH_ME_BIN |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 234 | default "" |
| 235 | help |
| 236 | Intel CSE CBFS RW blob path and file name |
V Sowmya | 187f06f | 2020-11-11 06:33:43 +0530 | [diff] [blame] | 237 | |
| 238 | config SOC_INTEL_CSE_RW_VERSION |
Subrata Banik | 3b0d573 | 2024-03-02 23:08:50 +0530 | [diff] [blame] | 239 | string "Intel CSE RW firmware version (deprecated)" if SOC_INTEL_CSE_RW_UPDATE |
V Sowmya | 187f06f | 2020-11-11 06:33:43 +0530 | [diff] [blame] | 240 | default "" |
| 241 | help |
| 242 | This config contains the Intel CSE RW version of the blob that is provided by |
| 243 | SOC_INTEL_CSE_RW_FILE config and the version must be set in the format |
| 244 | major.minor.hotfix.build (ex: 14.0.40.1209). |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 245 | |
Subrata Banik | 3b0d573 | 2024-03-02 23:08:50 +0530 | [diff] [blame] | 246 | This config may be deprecated in the future. Consider not providing the CSE RW |
| 247 | firmware version here and let the CSE version be automatically queried from the CSE |
| 248 | binary at build time (available with Meteor Lake and following platforms). |
| 249 | |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 250 | config SOC_INTEL_CSE_SET_EOP |
| 251 | bool |
| 252 | default n |
Tim Wawrzynczak | 9fdd2b2 | 2021-06-18 10:34:09 -0600 | [diff] [blame] | 253 | select PMC_IPC_ACPI_INTERFACE |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 254 | help |
| 255 | This config ensures coreboot will send the CSE the End-of-POST message |
| 256 | just prior to loading the payload. This is a security feature so the |
| 257 | CSE will no longer respond to Pre-Boot commands. |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 258 | |
Krishna Prasad Bhat | 333edcc | 2021-11-26 06:52:27 +0530 | [diff] [blame] | 259 | config SOC_INTEL_CSE_SUB_PART_UPDATE |
| 260 | bool "Enable the CSE sub-partition update Feature" |
| 261 | default n |
| 262 | depends on SOC_INTEL_CSE_LITE_SKU |
| 263 | help |
| 264 | This config will enable CSE sub-partition firmware update feature and also will be used ensure |
| 265 | all the required configs are provided by mainboard. |
| 266 | |
| 267 | config SOC_INTEL_CSE_IOM_CBFS_NAME |
| 268 | string "CBFS name for CSE sub-partition IOM binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 269 | default "cse_iom" |
| 270 | help |
| 271 | CBFS entry name for Intel CSE sub-partition IOM binary |
| 272 | |
| 273 | config SOC_INTEL_CSE_IOM_CBFS_FILE |
| 274 | string "Intel CBFS path and file name for CSE sub-partition IOM binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 275 | default "" |
| 276 | help |
| 277 | CBFS path and file name for Intel CSE sub-partition IOM binary |
| 278 | |
| 279 | config SOC_INTEL_CSE_NPHY_CBFS_NAME |
| 280 | string "CBFS name for CSE sub-partition NPHY binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 281 | default "cse_nphy" |
| 282 | help |
| 283 | CBFS entry name for Intel CSE sub-partition NPHY binary |
| 284 | |
| 285 | config SOC_INTEL_CSE_NPHY_CBFS_FILE |
| 286 | string "Intel CBFS path and file name for CSE sub-partition NPHY binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 287 | default "" |
| 288 | help |
| 289 | CBFS path and file name for Intel CSE sub-partition NPHY binary |
| 290 | |
Krishna Prasad Bhat | a67a92e | 2022-02-25 10:45:55 +0530 | [diff] [blame] | 291 | config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW |
| 292 | bool |
| 293 | default n |
| 294 | depends on SOC_INTEL_CSE_LITE_SKU |
Julius Werner | 6e303aa | 2023-05-25 18:26:32 -0700 | [diff] [blame] | 295 | select CBFS_ALLOW_UNVERIFIED_DECOMPRESSION if CBFS_VERIFICATION && !VBOOT_CBFS_INTEGRATION |
Krishna Prasad Bhat | a67a92e | 2022-02-25 10:45:55 +0530 | [diff] [blame] | 296 | help |
| 297 | Enable compression on Intel CSE CBFS RW blob |
| 298 | |
Bora Guvendik | 860672e | 2021-09-26 17:25:48 -0700 | [diff] [blame] | 299 | config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY |
| 300 | def_bool n |
| 301 | depends on SOC_INTEL_CSE_LITE_SKU |
| 302 | help |
| 303 | Mainboard user to select this Kconfig in order to capture pre-cpu |
| 304 | reset boot performance telemetry data. |
| 305 | |
Bora Guvendik | 9405049 | 2023-03-12 12:24:58 -0700 | [diff] [blame] | 306 | config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 |
| 307 | bool |
| 308 | select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY |
| 309 | help |
| 310 | This config will make mainboard use version 1 of the CSE timestamp |
| 311 | definitions, it can be used for Alder Lake and Raptor Lake (all SKUs). |
| 312 | |
| 313 | config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 |
| 314 | bool |
| 315 | select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY |
| 316 | help |
| 317 | This config will make mainboard use version 2 of the CSE timestamp |
| 318 | definitions, it can be used for Meteor Lake M/P. |
| 319 | |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 320 | config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE |
| 321 | bool |
Subrata Banik | 792ce81 | 2023-04-28 00:52:23 +0530 | [diff] [blame] | 322 | default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 323 | depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW |
| 324 | help |
| 325 | Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. |
| 326 | |
| 327 | config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE |
| 328 | bool |
| 329 | default n |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 330 | help |
Anil Kumar | afb926a | 2023-04-26 11:31:20 -0700 | [diff] [blame] | 331 | Use this option if CSE RW update needs to be triggered during RAMSTAGE. |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 332 | |
Dinesh Gehlot | 73fcbf1 | 2023-02-20 06:18:23 +0000 | [diff] [blame] | 333 | config SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 334 | bool |
| 335 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 336 | default n |
| 337 | help |
| 338 | This option config will allow SoC platform to use applicable ME specification. |
| 339 | The version based CSE measured ME specification data structures are defined at |
| 340 | common code. Enabling this option will use those CSE defined ME specification |
| 341 | for the SoC. User should select pertinent ME spec version along with this option. |
| 342 | |
| 343 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 |
| 344 | bool |
| 345 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 346 | help |
| 347 | This config will enable 'ME specification version 12'. It will ensure ME specific |
| 348 | declaration and uses of required data structures for Host firmware status registers. |
| 349 | |
| 350 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 |
| 351 | bool |
| 352 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 353 | help |
| 354 | This config will enable 'ME specification version 13'. It will ensure ME specific |
| 355 | declaration and uses of required data structures for Host firmware status registers. |
| 356 | |
| 357 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 |
| 358 | bool |
| 359 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 360 | help |
| 361 | This config will enable 'ME specification version 15'. It will ensure ME specific |
| 362 | declaration and uses of required data structures for Host firmware status registers. |
| 363 | |
| 364 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 |
| 365 | bool |
| 366 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 367 | help |
| 368 | This config will enable 'ME specification version 16'. It will ensure ME specific |
| 369 | declaration and uses of required data structures for Host firmware status registers. |
| 370 | |
| 371 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 |
| 372 | bool |
| 373 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 374 | help |
| 375 | This config will enable 'ME specification version 18'. It will ensure ME specific |
| 376 | declaration and uses of required data structures for Host firmware status registers. |
| 377 | |
| 378 | if SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 379 | |
| 380 | config ME_SPEC |
| 381 | int |
| 382 | default 12 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 |
| 383 | default 13 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 |
| 384 | default 15 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 |
| 385 | default 16 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 |
| 386 | default 18 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 |
| 387 | help |
| 388 | This config holds the ME spec version if defined. |
| 389 | |
| 390 | endif # SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 391 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 392 | if STITCH_ME_BIN |
| 393 | |
| 394 | config CSE_COMPONENTS_PATH |
| 395 | string "Path to directory containing all CSE input components to stitch" |
| 396 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/firmware" |
| 397 | help |
| 398 | This is the file path containing all the input CSE component files. |
| 399 | These will be used by cse_serger tool to stitch CSE image. |
| 400 | |
| 401 | config CSE_FPT_FILE |
| 402 | string "Name of CSE FPT file" |
| 403 | default "cse_fpt.bin" |
| 404 | help |
| 405 | This file is the CSE input binary as released by Intel in a CSE kit. |
| 406 | |
| 407 | config CSE_DATA_FILE |
| 408 | string "Name of CSE data file" |
| 409 | default "cse_data.bin" |
| 410 | help |
| 411 | This file is the CSE data binary typically generated by Intel FIT tool. |
| 412 | |
Reka Norman | 8d357b5 | 2023-08-07 06:49:32 +0000 | [diff] [blame] | 413 | config CSE_PMCP_FILE |
| 414 | string "Name of PMC file" |
| 415 | default "pmc.bin" |
| 416 | help |
| 417 | This file is the PMC input binary as released by Intel in a CSE kit. |
| 418 | |
| 419 | config CSE_IOMP_FILE |
| 420 | string "Name of IOM file" |
| 421 | default "iom.bin" |
| 422 | help |
| 423 | This file is the IOM input binary as released by Intel in a CSE kit. |
| 424 | |
| 425 | config CSE_TBTP_FILE |
| 426 | string "Name of TBT file" |
| 427 | default "tbt.bin" |
| 428 | help |
| 429 | This file is the TBT input binary as released by Intel in a CSE kit. |
| 430 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 431 | config CSE_NPHY_FILE |
| 432 | string "Name of NPHY file" |
| 433 | default "nphy.bin" |
| 434 | help |
| 435 | This file is the NPHY input binary as released by Intel in a CSE kit. |
| 436 | |
Reka Norman | 8d357b5 | 2023-08-07 06:49:32 +0000 | [diff] [blame] | 437 | config CSE_PCHC_FILE |
| 438 | string "Name of PCHC file" |
| 439 | default "pchc.bin" |
| 440 | help |
| 441 | This file is the PCHC input binary as released by Intel in a CSE kit. |
| 442 | |
| 443 | config CSE_IUNP_FILE |
| 444 | string "Name of IUNIT file" |
| 445 | default "iunit.bin" |
| 446 | help |
| 447 | This file is the PCHC input binary as released by Intel in a CSE kit. |
| 448 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 449 | config CSE_BPDT_VERSION |
| 450 | string |
| 451 | help |
| 452 | This config indicates the BPDT version used by CSE for a given SoC. |
| 453 | |
Reka Norman | 8d357b5 | 2023-08-07 06:49:32 +0000 | [diff] [blame] | 454 | config CSE_OEMP_FILE |
| 455 | string "Name of OEM Key Manifest file" |
| 456 | default "oem_km.bin" |
| 457 | help |
| 458 | OEM Key Manifest lists the public key hashes used for authenticating the |
| 459 | OEM created binaries to be loaded. This binary is generated by signing with |
| 460 | the key owned by trusted owner. |
| 461 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 462 | endif |
Derek Huang | 2189640 | 2023-09-01 07:55:40 +0000 | [diff] [blame] | 463 | |
| 464 | config CSE_RESET_CLEAR_EC_AP_IDLE_FLAG |
| 465 | bool |
| 466 | default y if !SYSTEM_TYPE_LAPTOP |
| 467 | help |
| 468 | Select this if the variant is a Chromebox/base. This allows AP to direct EC |
| 469 | to clear AP_IDLE flag before triggering reset to make sure AP can boot up |
| 470 | after reset. |