Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 5 | #include <soc/gpio.h> |
| 6 | |
| 7 | /* Early pad configuration in bootblock */ |
| 8 | static const struct pad_config early_gpio_table[] = { |
Cliff Huang | 82b7d0c | 2022-04-11 18:49:57 -0700 | [diff] [blame^] | 9 | /* WWAN_RST# (updated in ramstage) */ |
| 10 | PAD_CFG_GPO(GPP_F14, 0, DEEP), |
| 11 | /* WWAN_PERST_L (updated in ramstage) */ |
| 12 | PAD_CFG_GPO(GPP_C5, 0, DEEP), |
| 13 | /* WWAN_FCPO_L (updated in romstage) */ |
| 14 | PAD_CFG_GPO(GPP_F15, 0, DEEP), |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 15 | /* WWAN_PWR_EN */ |
Subrata Banik | 11f212b | 2020-11-12 20:31:42 +0530 | [diff] [blame] | 16 | PAD_CFG_GPO(GPP_F21, 1, DEEP), |
Subrata Banik | 486eabc | 2021-02-15 21:45:20 +0530 | [diff] [blame] | 17 | /* SMB_CLK */ |
| 18 | PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), |
| 19 | /* SMB_DATA */ |
| 20 | PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), |
Maulik V Vaghela | ce6fdd4 | 2021-04-12 22:35:17 +0530 | [diff] [blame] | 21 | |
Anil Kumar | 49ebce6 | 2021-10-04 10:11:54 -0700 | [diff] [blame] | 22 | /* EC_IN_RW */ |
| 23 | PAD_CFG_GPI(GPP_E7, NONE, DEEP), |
| 24 | |
Cliff Huang | 6c6be42 | 2022-04-28 18:38:44 -0700 | [diff] [blame] | 25 | /* x4 PCIE slot 1 RESET */ |
| 26 | PAD_CFG_GPO(GPP_F10, 0, PLTRST), |
| 27 | |
| 28 | /* Support external source clock via OEB6 and OEB7 */ |
| 29 | /* SRCCLK_OEB6 for built-in LAN */ |
| 30 | PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF2), |
| 31 | /* SRCCLK_OEB7 for x4 slot */ |
| 32 | PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), |
| 33 | |
Maulik V Vaghela | ce6fdd4 | 2021-04-12 22:35:17 +0530 | [diff] [blame] | 34 | /* CPU PCIe VGPIO for RP0 */ |
Kane Chen | 2a30359 | 2021-11-29 18:31:02 +0800 | [diff] [blame] | 35 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1), |
| 36 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1), |
| 37 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, PLTRST, NF1), |
| 38 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, PLTRST, NF1), |
| 39 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, PLTRST, NF1), |
| 40 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, PLTRST, NF1), |
| 41 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, PLTRST, NF1), |
| 42 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, PLTRST, NF1), |
| 43 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, PLTRST, NF1), |
| 44 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, PLTRST, NF1), |
| 45 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, PLTRST, NF1), |
| 46 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, PLTRST, NF1), |
| 47 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, PLTRST, NF1), |
| 48 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, PLTRST, NF1), |
| 49 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, PLTRST, NF1), |
| 50 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, PLTRST, NF1), |
| 51 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, PLTRST, NF1), |
| 52 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, PLTRST, NF1), |
| 53 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, PLTRST, NF1), |
| 54 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, PLTRST, NF1), |
Maulik V Vaghela | ce6fdd4 | 2021-04-12 22:35:17 +0530 | [diff] [blame] | 55 | |
| 56 | /* CPU PCIe vGPIO for RP1 */ |
Kane Chen | 2a30359 | 2021-11-29 18:31:02 +0800 | [diff] [blame] | 57 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, PLTRST, NF1), |
| 58 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, PLTRST, NF1), |
| 59 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, PLTRST, NF1), |
| 60 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, PLTRST, NF1), |
| 61 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, PLTRST, NF1), |
| 62 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, PLTRST, NF1), |
| 63 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, PLTRST, NF1), |
| 64 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, PLTRST, NF1), |
| 65 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, PLTRST, NF1), |
| 66 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, PLTRST, NF1), |
| 67 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, PLTRST, NF1), |
| 68 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, PLTRST, NF1), |
| 69 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, PLTRST, NF1), |
| 70 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, PLTRST, NF1), |
| 71 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, PLTRST, NF1), |
| 72 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, PLTRST, NF1), |
| 73 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, PLTRST, NF1), |
| 74 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, PLTRST, NF1), |
| 75 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, PLTRST, NF1), |
| 76 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, PLTRST, NF1), |
Maulik V Vaghela | ce6fdd4 | 2021-04-12 22:35:17 +0530 | [diff] [blame] | 77 | |
| 78 | /* CPU PCIe vGPIO for RP2 */ |
Kane Chen | 2a30359 | 2021-11-29 18:31:02 +0800 | [diff] [blame] | 79 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1), |
| 80 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1), |
| 81 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1), |
| 82 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1), |
| 83 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1), |
| 84 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1), |
| 85 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1), |
| 86 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1), |
| 87 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1), |
| 88 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1), |
| 89 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1), |
| 90 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1), |
| 91 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1), |
| 92 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1), |
| 93 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1), |
| 94 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1), |
| 95 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1), |
| 96 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1), |
| 97 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1), |
| 98 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1), |
Maulik V Vaghela | ce6fdd4 | 2021-04-12 22:35:17 +0530 | [diff] [blame] | 99 | |
| 100 | /* CPU PCIe vGPIO for RP3 */ |
Kane Chen | 2a30359 | 2021-11-29 18:31:02 +0800 | [diff] [blame] | 101 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), |
| 102 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), |
| 103 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), |
| 104 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), |
| 105 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), |
| 106 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), |
| 107 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), |
| 108 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), |
| 109 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), |
| 110 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), |
| 111 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), |
| 112 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), |
| 113 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), |
| 114 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), |
| 115 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), |
| 116 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), |
| 117 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), |
| 118 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), |
| 119 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), |
| 120 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 121 | }; |
| 122 | |
Michael Niewöhner | 2b58922 | 2020-12-21 03:46:58 +0100 | [diff] [blame] | 123 | static const struct pad_config early_uart_gpio_table[] = { |
| 124 | /* UART0 RX */ |
| 125 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 126 | /* UART0 TX */ |
| 127 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
| 128 | }; |
| 129 | |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 130 | void variant_configure_early_gpio_pads(void) |
| 131 | { |
Michael Niewöhner | 2b58922 | 2020-12-21 03:46:58 +0100 | [diff] [blame] | 132 | if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) |
| 133 | gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); |
| 134 | |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 135 | gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); |
| 136 | } |