Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 20 | #include <bootstate.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 21 | #include <cbmem.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <cpu/cpu.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <fsp/api.h> |
| 27 | #include <fsp/util.h> |
| 28 | #include <memrange.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 29 | #include <soc/iomap.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 30 | #include <soc/cpu.h> |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 31 | #include <soc/intel/common/vbt.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 32 | #include <soc/nvs.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 34 | #include <spi-generic.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 35 | #include <soc/pm.h> |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 36 | #include <soc/p2sb.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 37 | |
| 38 | #include "chip.h" |
| 39 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 40 | static void *vbt; |
| 41 | static struct region_device vbt_rdev; |
| 42 | |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 43 | static const char *soc_acpi_name(struct device *dev) |
| 44 | { |
| 45 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 46 | return "PCI0"; |
| 47 | |
| 48 | if (dev->path.type != DEVICE_PATH_PCI) |
| 49 | return NULL; |
| 50 | |
| 51 | switch (dev->path.pci.devfn) { |
| 52 | /* DSDT: acpi/northbridge.asl */ |
| 53 | case NB_DEVFN: |
| 54 | return "MCHC"; |
| 55 | /* DSDT: acpi/lpc.asl */ |
| 56 | case LPC_DEVFN: |
| 57 | return "LPCB"; |
| 58 | /* DSDT: acpi/xhci.asl */ |
| 59 | case XHCI_DEVFN: |
| 60 | return "XHCI"; |
| 61 | /* DSDT: acpi/pch_hda.asl */ |
| 62 | case HDA_DEVFN: |
| 63 | return "HDAS"; |
| 64 | /* DSDT: acpi/lpss.asl */ |
| 65 | case LPSS_DEVFN_UART0: |
| 66 | return "URT1"; |
| 67 | case LPSS_DEVFN_UART1: |
| 68 | return "URT2"; |
| 69 | case LPSS_DEVFN_UART2: |
| 70 | return "URT3"; |
| 71 | case LPSS_DEVFN_UART3: |
| 72 | return "URT4"; |
| 73 | case LPSS_DEVFN_SPI0: |
| 74 | return "SPI1"; |
| 75 | case LPSS_DEVFN_SPI1: |
| 76 | return "SPI2"; |
| 77 | case LPSS_DEVFN_SPI2: |
| 78 | return "SPI3"; |
| 79 | case LPSS_DEVFN_PWM: |
| 80 | return "PWM"; |
| 81 | case LPSS_DEVFN_I2C0: |
| 82 | return "I2C0"; |
| 83 | case LPSS_DEVFN_I2C1: |
| 84 | return "I2C1"; |
| 85 | case LPSS_DEVFN_I2C2: |
| 86 | return "I2C2"; |
| 87 | case LPSS_DEVFN_I2C3: |
| 88 | return "I2C3"; |
| 89 | case LPSS_DEVFN_I2C4: |
| 90 | return "I2C4"; |
| 91 | case LPSS_DEVFN_I2C5: |
| 92 | return "I2C5"; |
| 93 | case LPSS_DEVFN_I2C6: |
| 94 | return "I2C6"; |
| 95 | case LPSS_DEVFN_I2C7: |
| 96 | return "I2C7"; |
| 97 | /* Storage */ |
| 98 | case SDCARD_DEVFN: |
| 99 | return "SDCD"; |
| 100 | case EMMC_DEVFN: |
| 101 | return "EMMC"; |
| 102 | case SDIO_DEVFN: |
| 103 | return "SDIO"; |
| 104 | } |
| 105 | |
| 106 | return NULL; |
| 107 | } |
| 108 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 109 | static void pci_domain_set_resources(device_t dev) |
| 110 | { |
| 111 | assign_resources(dev->link_list); |
| 112 | } |
| 113 | |
| 114 | static struct device_operations pci_domain_ops = { |
| 115 | .read_resources = pci_domain_read_resources, |
| 116 | .set_resources = pci_domain_set_resources, |
| 117 | .enable_resources = NULL, |
| 118 | .init = NULL, |
| 119 | .scan_bus = pci_domain_scan_bus, |
| 120 | .ops_pci_bus = pci_bus_default_ops, |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 121 | .acpi_name = &soc_acpi_name, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | static struct device_operations cpu_bus_ops = { |
| 125 | .read_resources = DEVICE_NOOP, |
| 126 | .set_resources = DEVICE_NOOP, |
| 127 | .enable_resources = DEVICE_NOOP, |
| 128 | .init = apollolake_init_cpus, |
| 129 | .scan_bus = NULL, |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 130 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | static void enable_dev(device_t dev) |
| 134 | { |
| 135 | /* Set the operations if it is a special bus type */ |
| 136 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 137 | dev->ops = &pci_domain_ops; |
| 138 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 139 | dev->ops = &cpu_bus_ops; |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | static void soc_init(void *data) |
| 144 | { |
| 145 | struct range_entry range; |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 146 | struct global_nvs_t *gnvs; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 147 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 148 | /* Save VBT info and mapping */ |
| 149 | if (locate_vbt(&vbt_rdev) != CB_ERR) |
| 150 | vbt = rdev_mmap_full(&vbt_rdev); |
| 151 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 152 | /* TODO: tigten this resource range */ |
| 153 | /* TODO: fix for S3 resume, as this would corrupt OS memory */ |
| 154 | range_entry_init(&range, 0x200000, 4ULL*GiB, 0); |
| 155 | fsp_silicon_init(&range); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 156 | |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 157 | /* |
| 158 | * Keep the P2SB device visible so it and the other devices are |
| 159 | * visible in coreboot for driver support and PCI resource allocation. |
| 160 | * There is a UPD setting for this, but it's more consistent to use |
| 161 | * hide and unhide symmetrically. |
| 162 | */ |
| 163 | p2sb_unhide(); |
| 164 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 165 | /* Allocate ACPI NVS in CBMEM */ |
| 166 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 167 | } |
| 168 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 169 | static void soc_final(void *data) |
| 170 | { |
| 171 | if (vbt) |
| 172 | rdev_munmap(&vbt_rdev, vbt); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 173 | |
| 174 | /* Disable global reset, just in case */ |
| 175 | global_reset_enable(0); |
| 176 | /* Make sure payload/OS can't trigger global reset */ |
| 177 | global_reset_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 178 | } |
| 179 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 180 | static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) { |
| 181 | |
| 182 | switch (dev->path.pci.devfn) { |
| 183 | case ISH_DEVFN: |
| 184 | silconfig->IshEnable = 0; |
| 185 | break; |
| 186 | case SATA_DEVFN: |
| 187 | silconfig->EnableSata = 0; |
| 188 | break; |
| 189 | case PCIEA0_DEVFN: |
| 190 | silconfig->PcieRootPortEn[0] = 0; |
| 191 | break; |
| 192 | case PCIEA1_DEVFN: |
| 193 | silconfig->PcieRootPortEn[1] = 0; |
| 194 | break; |
| 195 | case PCIEA2_DEVFN: |
| 196 | silconfig->PcieRootPortEn[2] = 0; |
| 197 | break; |
| 198 | case PCIEA3_DEVFN: |
| 199 | silconfig->PcieRootPortEn[3] = 0; |
| 200 | break; |
| 201 | case PCIEB0_DEVFN: |
| 202 | silconfig->PcieRootPortEn[4] = 0; |
| 203 | break; |
| 204 | case PCIEB1_DEVFN: |
| 205 | silconfig->PcieRootPortEn[5] = 0; |
| 206 | break; |
| 207 | case XHCI_DEVFN: |
| 208 | silconfig->Usb30Mode = 0; |
| 209 | break; |
| 210 | case XDCI_DEVFN: |
| 211 | silconfig->UsbOtg = 0; |
| 212 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 213 | case LPSS_DEVFN_I2C0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 214 | silconfig->I2c0Enable = 0; |
| 215 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 216 | case LPSS_DEVFN_I2C1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 217 | silconfig->I2c1Enable = 0; |
| 218 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 219 | case LPSS_DEVFN_I2C2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 220 | silconfig->I2c2Enable = 0; |
| 221 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 222 | case LPSS_DEVFN_I2C3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 223 | silconfig->I2c3Enable = 0; |
| 224 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 225 | case LPSS_DEVFN_I2C4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 226 | silconfig->I2c4Enable = 0; |
| 227 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 228 | case LPSS_DEVFN_I2C5: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 229 | silconfig->I2c5Enable = 0; |
| 230 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 231 | case LPSS_DEVFN_I2C6: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 232 | silconfig->I2c6Enable = 0; |
| 233 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 234 | case LPSS_DEVFN_I2C7: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 235 | silconfig->I2c7Enable = 0; |
| 236 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 237 | case LPSS_DEVFN_UART0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 238 | silconfig->Hsuart0Enable = 0; |
| 239 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 240 | case LPSS_DEVFN_UART1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 241 | silconfig->Hsuart1Enable = 0; |
| 242 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 243 | case LPSS_DEVFN_UART2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 244 | silconfig->Hsuart2Enable = 0; |
| 245 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 246 | case LPSS_DEVFN_UART3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 247 | silconfig->Hsuart3Enable = 0; |
| 248 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 249 | case LPSS_DEVFN_SPI0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 250 | silconfig->Spi0Enable = 0; |
| 251 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 252 | case LPSS_DEVFN_SPI1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 253 | silconfig->Spi1Enable = 0; |
| 254 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 255 | case LPSS_DEVFN_SPI2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 256 | silconfig->Spi2Enable = 0; |
| 257 | break; |
| 258 | case SDCARD_DEVFN: |
| 259 | silconfig->SdcardEnabled = 0; |
| 260 | break; |
| 261 | case EMMC_DEVFN: |
| 262 | silconfig->eMMCEnabled = 0; |
| 263 | break; |
| 264 | case SDIO_DEVFN: |
| 265 | silconfig->SdioEnabled = 0; |
| 266 | break; |
| 267 | case SMBUS_DEVFN: |
| 268 | silconfig->SmbusEnable = 0; |
| 269 | break; |
| 270 | default: |
| 271 | printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", |
| 272 | PCI_SLOT(dev->path.pci.devfn), |
| 273 | PCI_FUNC(dev->path.pci.devfn)); |
| 274 | break; |
| 275 | } |
| 276 | } |
| 277 | |
| 278 | static void parse_devicetree(struct FSP_S_CONFIG *silconfig) |
| 279 | { |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 280 | struct device *dev = NB_DEV_ROOT; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 281 | |
| 282 | if (!dev) { |
| 283 | printk(BIOS_ERR, "Could not find root device\n"); |
| 284 | return; |
| 285 | } |
| 286 | /* Only disable bus 0 devices. */ |
| 287 | for (dev = dev->bus->children; dev; dev = dev->sibling) { |
| 288 | if (!dev->enabled) |
| 289 | disable_dev(dev, silconfig); |
| 290 | } |
| 291 | } |
| 292 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 293 | void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) |
| 294 | { |
| 295 | struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
| 296 | static struct soc_intel_apollolake_config *cfg; |
| 297 | |
| 298 | /* Load VBT before devicetree-specific config. */ |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 299 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 300 | |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 301 | struct device *dev = NB_DEV_ROOT; |
| 302 | |
Patrick Georgi | 831d65d | 2016-04-14 11:53:48 +0200 | [diff] [blame] | 303 | if (!dev || !dev->chip_info) { |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 304 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 305 | return; |
| 306 | } |
| 307 | |
| 308 | cfg = dev->chip_info; |
| 309 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 310 | /* Parse device tree and disable unused device*/ |
| 311 | parse_devicetree(silconfig); |
| 312 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 313 | silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; |
| 314 | silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; |
| 315 | silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; |
| 316 | silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; |
| 317 | silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; |
| 318 | silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 319 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 320 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 321 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 322 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 323 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 324 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 325 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 326 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 327 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 328 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 329 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 330 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 331 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
| 332 | |
Hannah Williams | 483004f | 2016-03-28 14:45:59 -0700 | [diff] [blame] | 333 | silconfig->IshEnable = cfg->integrated_sensor_hub_enable; |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 334 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 335 | silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |
| 336 | |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 337 | /* Disable setting of EISS bit in FSP. */ |
| 338 | silconfig->SpiEiss = 0; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 339 | } |
| 340 | |
| 341 | struct chip_operations soc_intel_apollolake_ops = { |
| 342 | CHIP_NAME("Intel Apollolake SOC") |
| 343 | .enable_dev = &enable_dev, |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 344 | .init = &soc_init, |
| 345 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 346 | }; |
| 347 | |
| 348 | static void fsp_notify_dummy(void *arg) |
| 349 | { |
| 350 | |
| 351 | enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; |
Andrey Petrov | 1973c39 | 2016-06-22 19:32:51 -0700 | [diff] [blame] | 352 | enum fsp_status ret; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 353 | |
Andrey Petrov | 1973c39 | 2016-06-22 19:32:51 -0700 | [diff] [blame] | 354 | if ((ret = fsp_notify(ph)) != FSP_SUCCESS) { |
| 355 | printk(BIOS_CRIT, "FspNotify failed, ret = %x!\n", ret); |
| 356 | if (fsp_reset_requested(ret)) |
| 357 | fsp_handle_reset(ret); |
| 358 | } |
Hannah Williams | 5d9cc78 | 2016-04-29 14:48:20 -0700 | [diff] [blame] | 359 | /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 360 | if (ph == READY_TO_BOOT) { |
Hannah Williams | 5d9cc78 | 2016-04-29 14:48:20 -0700 | [diff] [blame] | 361 | fsp_notify_dummy((void *)END_OF_FIRMWARE); |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 362 | /* Hide the P2SB device to align with previous behavior. */ |
| 363 | p2sb_hide(); |
| 364 | } |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, |
| 368 | (void *) AFTER_PCI_ENUM); |
| 369 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, |
| 370 | (void *) READY_TO_BOOT); |
| 371 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, |
| 372 | (void *) READY_TO_BOOT); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 373 | |
| 374 | /* |
| 375 | * spi_init() needs to run unconditionally on every boot (including resume) to |
| 376 | * allow write protect to be disabled for eventlog and nvram updates. This needs |
| 377 | * to be done as early as possible in ramstage. Thus, add a callback for entry |
| 378 | * into BS_PRE_DEVICE. |
| 379 | */ |
| 380 | static void spi_init_cb(void *unused) |
| 381 | { |
| 382 | spi_init(); |
| 383 | } |
| 384 | |
| 385 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL); |