Angel Pons | 585495e | 2020-04-03 01:21:38 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 2 | |
| 3 | #include <device/device.h> |
| 4 | #include <device/pci.h> |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
| 6 | #include <pc80/keyboard.h> |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 7 | |
Angel Pons | 816a41c | 2021-01-28 11:09:56 +0100 | [diff] [blame^] | 8 | #include "q35.h" |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 9 | |
| 10 | static const unsigned char qemu_q35_irqs[] = { |
| 11 | 10, 10, 11, 11, |
| 12 | 10, 10, 11, 11, |
| 13 | }; |
| 14 | |
Elyes HAOUAS | 5cb876c | 2018-06-08 18:31:43 +0200 | [diff] [blame] | 15 | static void qemu_nb_init(struct device *dev) |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 16 | { |
| 17 | /* Map memory at 0xc0000 - 0xfffff */ |
| 18 | int i; |
Angel Pons | 816a41c | 2021-01-28 11:09:56 +0100 | [diff] [blame^] | 19 | uint8_t v = pci_read_config8(dev, D0F0_PAM(0)); |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 20 | v |= 0x30; |
Angel Pons | 816a41c | 2021-01-28 11:09:56 +0100 | [diff] [blame^] | 21 | pci_write_config8(dev, D0F0_PAM(0), v); |
| 22 | pci_write_config8(dev, D0F0_PAM(1), 0x33); |
| 23 | pci_write_config8(dev, D0F0_PAM(2), 0x33); |
| 24 | pci_write_config8(dev, D0F0_PAM(3), 0x33); |
| 25 | pci_write_config8(dev, D0F0_PAM(4), 0x33); |
| 26 | pci_write_config8(dev, D0F0_PAM(5), 0x33); |
| 27 | pci_write_config8(dev, D0F0_PAM(6), 0x33); |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 28 | |
Paul Menzel | feecdc2 | 2020-06-20 23:01:37 +0200 | [diff] [blame] | 29 | /* This sneaked in here, because Qemu does not emulate a SuperIO chip. */ |
Timothy Pearson | 448e386 | 2015-11-24 14:12:01 -0600 | [diff] [blame] | 30 | pc_keyboard_init(NO_AUX_DEVICE); |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 31 | |
| 32 | /* setup IRQ routing for pci slots */ |
| 33 | for (i = 0; i < 25; i++) |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 34 | pci_assign_irqs(pcidev_on_root(i, 0), qemu_q35_irqs + (i % 4)); |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 35 | /* setup IRQ routing southbridge devices */ |
| 36 | for (i = 25; i < 32; i++) |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 37 | pci_assign_irqs(pcidev_on_root(i, 0), qemu_q35_irqs); |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | static void qemu_nb_read_resources(struct device *dev) |
| 41 | { |
| 42 | pci_dev_read_resources(dev); |
| 43 | |
| 44 | /* reserve mmconfig */ |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 45 | fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10, |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 46 | IORESOURCE_RESERVE); |
Patrick Rudolph | 82e111c | 2021-01-07 14:12:38 +0100 | [diff] [blame] | 47 | |
| 48 | if (CONFIG(ARCH_RAMSTAGE_X86_64)) { |
| 49 | /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */ |
| 50 | reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB, |
| 51 | (6 * 0x1000) / KiB); |
| 52 | } |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | |
| 56 | static struct device_operations nb_operations = { |
| 57 | .read_resources = qemu_nb_read_resources, |
| 58 | .set_resources = pci_dev_set_resources, |
| 59 | .enable_resources = pci_dev_enable_resources, |
| 60 | .init = qemu_nb_init, |
Gerd Hoffmann | ee941b38 | 2013-06-07 16:03:44 +0200 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | static const struct pci_driver nb_driver __pci_driver = { |
| 64 | .ops = &nb_operations, |
| 65 | .vendor = 0x8086, |
| 66 | .device = 0x29c0, |
| 67 | }; |