Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/cpu.h> |
| 18 | #include <arch/acpi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 19 | #include <bootstate.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | #include <cbmem.h> |
| 21 | #include <console/console.h> |
| 22 | #include <cpu/intel/microcode.h> |
| 23 | #include <cpu/x86/cr.h> |
| 24 | #include <cpu/x86/msr.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci_def.h> |
| 27 | #include <device/pci_ops.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 28 | #include <fsp/util.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 29 | #include <soc/gpio.h> |
| 30 | #include <soc/lpc.h> |
| 31 | #include <soc/msr.h> |
| 32 | #include <soc/nvs.h> |
| 33 | #include <soc/pattrs.h> |
| 34 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 35 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 36 | #include <soc/ramstage.h> |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 37 | #include <soc/intel/common/acpi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 38 | #include <boardid.h> |
| 39 | #include <stdlib.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 40 | |
| 41 | #define SHOW_PATTRS 1 |
| 42 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 43 | struct pattrs __global_pattrs; |
| 44 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 45 | static void detect_num_cpus(struct pattrs *attrs) |
| 46 | { |
| 47 | int ecx = 0; |
| 48 | |
| 49 | while (1) { |
| 50 | struct cpuid_result leaf_b; |
| 51 | |
| 52 | leaf_b = cpuid_ext(0xb, ecx); |
| 53 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 54 | /* |
| 55 | * The SOC doesn't have hyperthreading so just determine the |
| 56 | * number of cores by from level type (ecx[15:8] == * 2). |
| 57 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 58 | if ((leaf_b.ecx & 0xff00) == 0x0200) { |
| 59 | attrs->num_cpus = leaf_b.ebx & 0xffff; |
| 60 | break; |
| 61 | } |
| 62 | ecx++; |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | static inline void fill_in_msr(msr_t *msr, int idx) |
| 67 | { |
| 68 | *msr = rdmsr(idx); |
| 69 | if (SHOW_PATTRS) { |
| 70 | printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", |
| 71 | idx, msr->hi, msr->lo); |
| 72 | } |
| 73 | } |
| 74 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 75 | static const char * const stepping_str[] = { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 76 | "A0", "A1", "B0", "B1", "B2", "B3", "C0" |
| 77 | }; |
| 78 | |
| 79 | static void fill_in_pattrs(void) |
| 80 | { |
| 81 | device_t dev; |
| 82 | msr_t msr; |
| 83 | struct pattrs *attrs = (struct pattrs *)pattrs_get(); |
| 84 | |
| 85 | attrs->cpuid = cpuid_eax(1); |
| 86 | dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); |
| 87 | attrs->revid = pci_read_config8(dev, REVID); |
| 88 | /* The revision to stepping IDs have two values per metal stepping. */ |
| 89 | if (attrs->revid >= RID_C_STEPPING_START) { |
| 90 | attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; |
| 91 | attrs->stepping += STEP_C0; |
| 92 | } else if (attrs->revid >= RID_B_STEPPING_START) { |
| 93 | attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; |
| 94 | attrs->stepping += STEP_B0; |
| 95 | } else { |
| 96 | attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; |
| 97 | attrs->stepping += STEP_A0; |
| 98 | } |
| 99 | |
| 100 | attrs->microcode_patch = intel_microcode_find(); |
| 101 | attrs->address_bits = cpuid_eax(0x80000008) & 0xff; |
| 102 | detect_num_cpus(attrs); |
| 103 | |
| 104 | if (SHOW_PATTRS) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 105 | printk(BIOS_DEBUG, "Cpuid %08x cpus %d rid %02x step %s\n", |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 106 | attrs->cpuid, attrs->num_cpus, attrs->revid, |
| 107 | (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : |
| 108 | stepping_str[attrs->stepping]); |
| 109 | } |
| 110 | |
| 111 | fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); |
| 112 | fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); |
| 113 | |
| 114 | /* Set IA core speed ratio and voltages */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 115 | fill_in_msr(&msr, MSR_IACORE_RATIOS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 116 | attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; |
| 117 | attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; |
| 118 | attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 119 | fill_in_msr(&msr, MSR_IACORE_TURBO_RATIOS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 120 | attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ |
| 121 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 122 | fill_in_msr(&msr, MSR_IACORE_VIDS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 123 | attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; |
| 124 | attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; |
| 125 | attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 126 | fill_in_msr(&msr, MSR_IACORE_TURBO_VIDS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 127 | attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ |
| 128 | |
| 129 | /* Set bus clock speed */ |
Subrata Banik | 45a221d | 2015-08-05 17:01:55 +0530 | [diff] [blame] | 130 | attrs->bclk_khz = cpu_bus_freq_khz(); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 133 | /* Save wake source information for calculating ACPI _SWS values */ |
| 134 | int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 135 | { |
| 136 | struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 137 | static uint32_t gpe0_sts; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 138 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 139 | *pm1 = ps->pm1_sts & ps->pm1_en; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 140 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 141 | gpe0_sts = ps->gpe0_sts & ps->gpe0_en; |
| 142 | *gpe0 = &gpe0_sts; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 143 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 144 | return 1; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | static void s3_resume_prepare(void) |
| 148 | { |
| 149 | global_nvs_t *gnvs; |
| 150 | |
| 151 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Aaron Durbin | 0dca649 | 2016-07-13 11:54:12 -0500 | [diff] [blame] | 152 | if (!acpi_is_wakeup_s3() && gnvs) |
| 153 | memset(gnvs, 0, sizeof(global_nvs_t)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 154 | } |
| 155 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 156 | static void set_board_id(void) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 157 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 158 | global_nvs_t *gnvs; |
| 159 | |
| 160 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 161 | if (!gnvs) { |
| 162 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 163 | return; |
| 164 | } |
| 165 | gnvs->bdid = board_id(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 166 | } |
| 167 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 168 | void soc_init_pre_device(struct soc_intel_braswell_config *config) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 169 | { |
| 170 | struct soc_gpio_config *gpio_config; |
| 171 | |
| 172 | fill_in_pattrs(); |
| 173 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 174 | /* Allow for SSE instructions to be executed. */ |
| 175 | write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); |
| 176 | |
| 177 | /* Indicate S3 resume to rest of ramstage. */ |
| 178 | s3_resume_prepare(); |
| 179 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 180 | /* Perform silicon specific init. */ |
| 181 | intel_silicon_init(); |
Hannah Williams | b0eb594 | 2015-08-23 17:24:43 -0700 | [diff] [blame] | 182 | set_max_freq(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 183 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 184 | set_board_id(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 185 | /* Get GPIO initial states from mainboard */ |
| 186 | gpio_config = mainboard_get_gpios(); |
| 187 | setup_soc_gpios(gpio_config, config->enable_xdp_tap); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 188 | } |