Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 17 | /* |
| 18 | * The devicetree parser expects chip.h to reside directly in the path |
| 19 | * specified by the devicetree. |
| 20 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 22 | #ifndef _SOC_CHIP_H_ |
| 23 | #define _SOC_CHIP_H_ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 24 | |
| 25 | #include <stdint.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 26 | #include <fsp/util.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 28 | |
Jenny TC | 153ae10 | 2015-06-18 14:55:10 +0530 | [diff] [blame] | 29 | #define SVID_CONFIG1 1 |
| 30 | #define SVID_CONFIG3 3 |
| 31 | #define SVID_PMIC_CONFIG 8 |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 32 | |
Jenny TC | 5468e94 | 2015-06-18 14:02:00 +0530 | [diff] [blame] | 33 | #define MEM_DDR3 0 |
| 34 | #define MEM_LPDDR3 1 |
| 35 | |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 36 | enum lpe_clk_src { |
| 37 | LPE_CLK_SRC_XTAL, |
| 38 | LPE_CLK_SRC_PLL, |
| 39 | }; |
| 40 | |
shkim | cc728f0 | 2015-09-22 17:53:58 +0900 | [diff] [blame] | 41 | enum usb_comp_bg_value { |
| 42 | USB_COMP_BG_575_MV = 7, |
| 43 | USB_COMP_BG_650_MV = 6, |
| 44 | USB_COMP_BG_550_MV = 5, |
| 45 | USB_COMP_BG_537_MV = 4, |
| 46 | USB_COMP_BG_625_MV = 3, |
| 47 | USB_COMP_BG_700_MV = 2, |
| 48 | USB_COMP_BG_600_MV = 1, |
| 49 | USB_COMP_BG_675_MV = 0, |
| 50 | }; |
| 51 | |
| 52 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 53 | struct soc_intel_braswell_config { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 54 | uint8_t enable_xdp_tap; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 55 | uint8_t clkreq_enable; |
| 56 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 57 | /* Disable SLP_X stretching after SUS power well loss. */ |
| 58 | int disable_slp_x_stretch_sus_fail; |
| 59 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 60 | /* LPE Audio Clock configuration. */ |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 61 | enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 62 | |
| 63 | /* Native SD Card controller - override controller capabilities. */ |
| 64 | uint32_t sdcard_cap_low; |
| 65 | uint32_t sdcard_cap_high; |
| 66 | |
| 67 | /* Enable devices in ACPI mode */ |
| 68 | int lpss_acpi_mode; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 69 | int emmc_acpi_mode; |
| 70 | int sd_acpi_mode; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 71 | int lpe_acpi_mode; |
| 72 | |
| 73 | /* Allow PCIe devices to wake system from suspend. */ |
| 74 | int pcie_wake_enable; |
| 75 | |
shkim | cc728f0 | 2015-09-22 17:53:58 +0900 | [diff] [blame] | 76 | /* Program USB2_COMPBG register. |
| 77 | * [10:7] - select vref to AFE port |
| 78 | * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV, |
| 79 | * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV |
| 80 | */ |
| 81 | enum usb_comp_bg_value usb_comp_bg; |
| 82 | |
| 83 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 84 | /* |
| 85 | * The following fields come from fsp_vpd.h .aka. VpdHeader.h. |
| 86 | * These are configuration values that are passed to FSP during |
| 87 | * MemoryInit. |
| 88 | */ |
| 89 | UINT16 PcdMrcInitTsegSize; |
| 90 | UINT16 PcdMrcInitMmioSize; |
| 91 | UINT8 PcdMrcInitSpdAddr1; |
| 92 | UINT8 PcdMrcInitSpdAddr2; |
| 93 | UINT8 PcdIgdDvmt50PreAlloc; |
| 94 | UINT8 PcdApertureSize; |
| 95 | UINT8 PcdGttSize; |
| 96 | UINT8 PcdLegacySegDecode; |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 97 | UINT8 PcdDvfsEnable; |
Shobhit Srivastava | c4153c1 | 2015-10-09 17:05:16 +0530 | [diff] [blame] | 98 | UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 99 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 100 | /* |
| 101 | * The following fields come from fsp_vpd.h .aka. VpdHeader.h. |
| 102 | * These are configuration values that are passed to FSP during |
| 103 | * SiliconInit. |
| 104 | */ |
| 105 | UINT8 PcdSdcardMode; |
| 106 | UINT8 PcdEnableHsuart0; |
| 107 | UINT8 PcdEnableHsuart1; |
| 108 | UINT8 PcdEnableAzalia; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 109 | UINT8 PcdEnableSata; |
| 110 | UINT8 PcdEnableXhci; |
| 111 | UINT8 PcdEnableLpe; |
| 112 | UINT8 PcdEnableDma0; |
| 113 | UINT8 PcdEnableDma1; |
| 114 | UINT8 PcdEnableI2C0; |
| 115 | UINT8 PcdEnableI2C1; |
| 116 | UINT8 PcdEnableI2C2; |
| 117 | UINT8 PcdEnableI2C3; |
| 118 | UINT8 PcdEnableI2C4; |
| 119 | UINT8 PcdEnableI2C5; |
| 120 | UINT8 PcdEnableI2C6; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 121 | UINT8 PunitPwrConfigDisable; |
| 122 | UINT8 ChvSvidConfig; |
| 123 | UINT8 DptfDisable; |
| 124 | UINT8 PcdEmmcMode; |
| 125 | UINT8 PcdUsb3ClkSsc; |
| 126 | UINT8 PcdDispClkSsc; |
| 127 | UINT8 PcdSataClkSsc; |
| 128 | UINT8 Usb2Port0PerPortPeTxiSet; |
| 129 | UINT8 Usb2Port0PerPortTxiSet; |
| 130 | UINT8 Usb2Port0IUsbTxEmphasisEn; |
| 131 | UINT8 Usb2Port0PerPortTxPeHalf; |
| 132 | UINT8 Usb2Port1PerPortPeTxiSet; |
| 133 | UINT8 Usb2Port1PerPortTxiSet; |
| 134 | UINT8 Usb2Port1IUsbTxEmphasisEn; |
| 135 | UINT8 Usb2Port1PerPortTxPeHalf; |
| 136 | UINT8 Usb2Port2PerPortPeTxiSet; |
| 137 | UINT8 Usb2Port2PerPortTxiSet; |
| 138 | UINT8 Usb2Port2IUsbTxEmphasisEn; |
| 139 | UINT8 Usb2Port2PerPortTxPeHalf; |
| 140 | UINT8 Usb2Port3PerPortPeTxiSet; |
| 141 | UINT8 Usb2Port3PerPortTxiSet; |
| 142 | UINT8 Usb2Port3IUsbTxEmphasisEn; |
| 143 | UINT8 Usb2Port3PerPortTxPeHalf; |
| 144 | UINT8 Usb2Port4PerPortPeTxiSet; |
| 145 | UINT8 Usb2Port4PerPortTxiSet; |
| 146 | UINT8 Usb2Port4IUsbTxEmphasisEn; |
| 147 | UINT8 Usb2Port4PerPortTxPeHalf; |
| 148 | UINT8 Usb3Lane0Ow2tapgen2deemph3p5; |
| 149 | UINT8 Usb3Lane1Ow2tapgen2deemph3p5; |
| 150 | UINT8 Usb3Lane2Ow2tapgen2deemph3p5; |
| 151 | UINT8 Usb3Lane3Ow2tapgen2deemph3p5; |
| 152 | UINT8 PcdSataInterfaceSpeed; |
| 153 | UINT8 PcdPchUsbSsicPort; |
| 154 | UINT8 PcdPchUsbHsicPort; |
| 155 | UINT8 PcdPcieRootPortSpeed; |
| 156 | UINT8 PcdPchSsicEnable; |
| 157 | UINT32 PcdLogoPtr; |
| 158 | UINT32 PcdLogoSize; |
| 159 | UINT8 PcdRtcLock; |
| 160 | UINT8 PMIC_I2CBus; |
| 161 | UINT8 ISPEnable; |
| 162 | UINT8 ISPPciDevConfig; |
Divya Sasidharan | 89a6685 | 2015-10-28 15:02:35 -0700 | [diff] [blame] | 163 | UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 164 | }; |
| 165 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 166 | extern struct chip_operations soc_intel_braswell_ops; |
| 167 | |
| 168 | #endif /* _SOC_CHIP_H_ */ |