Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 2 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi_device.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 7 | #include <device/i2c_simple.h> |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 8 | #include <drivers/i2c/designware/dw_i2c.h> |
Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 9 | #include <drivers/intel/gma/gma.h> |
Dinesh Gehlot | 770a46c | 2023-01-17 05:54:17 +0000 | [diff] [blame] | 10 | #include <gpio.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 11 | #include <intelblocks/cfg.h> |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 12 | #include <intelblocks/gspi.h> |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 13 | #include <intelblocks/lpc_lib.h> |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 14 | #include <intelblocks/power_limit.h> |
Reka Norman | a5215c4 | 2023-09-22 15:26:54 +1000 | [diff] [blame] | 15 | #include <intelblocks/xhci.h> |
Felix Singer | 743242b | 2023-06-16 01:33:25 +0200 | [diff] [blame] | 16 | #include <stdbool.h> |
Aaron Durbin | 9a8dc37 | 2015-08-07 22:29:42 -0500 | [diff] [blame] | 17 | #include <stdint.h> |
Duncan Laurie | 011533e | 2016-05-11 15:08:50 -0700 | [diff] [blame] | 18 | #include <soc/gpe.h> |
Barnali Sarkar | 8f2f22d | 2016-08-03 12:15:22 +0530 | [diff] [blame] | 19 | #include <soc/irq.h> |
Aaron Durbin | 9a8dc37 | 2015-08-07 22:29:42 -0500 | [diff] [blame] | 20 | #include <soc/pci_devs.h> |
| 21 | #include <soc/pmc.h> |
| 22 | #include <soc/serialio.h> |
Duncan Laurie | fe86666 | 2015-10-16 13:58:11 -0700 | [diff] [blame] | 23 | #include <soc/usb.h> |
Rizwan Qureshi | 2b1e8b3 | 2015-11-20 11:46:54 +0530 | [diff] [blame] | 24 | #include <soc/vr_config.h> |
Aaron Durbin | 9a8dc37 | 2015-08-07 22:29:42 -0500 | [diff] [blame] | 25 | |
Maxim Polyakov | 0220d1e | 2019-03-18 17:38:44 +0300 | [diff] [blame] | 26 | #define MAX_PEG_PORTS 3 |
| 27 | |
Duncan Laurie | c8d45ac | 2016-06-06 17:21:00 -0700 | [diff] [blame] | 28 | enum skylake_i2c_voltage { |
| 29 | I2C_VOLTAGE_3V3, |
| 30 | I2C_VOLTAGE_1V8 |
| 31 | }; |
| 32 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 33 | struct soc_intel_skylake_config { |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 34 | |
| 35 | /* Common struct containing soc config data required by common code */ |
| 36 | struct soc_intel_common_config common_soc_config; |
| 37 | |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 38 | /* Common struct containing power limits configuration information */ |
| 39 | struct soc_power_limits_config power_limits_config; |
| 40 | |
Nico Huber | 1a65017 | 2018-12-16 02:39:28 +0100 | [diff] [blame] | 41 | /* IGD panel configuration */ |
Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 42 | struct i915_gpu_panel_config panel_cfg; |
Nico Huber | 1a65017 | 2018-12-16 02:39:28 +0100 | [diff] [blame] | 43 | |
Aaron Durbin | 9a8dc37 | 2015-08-07 22:29:42 -0500 | [diff] [blame] | 44 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 45 | * of the form GPP_[A:G] or GPD. */ |
| 46 | uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 47 | uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 48 | uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 49 | |
Wim Vervoorn | 5f2adfe | 2020-02-03 15:32:54 +0100 | [diff] [blame] | 50 | /* LPC fixed enables and ranges */ |
| 51 | uint16_t lpc_iod; |
| 52 | uint16_t lpc_ioe; |
| 53 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 54 | /* Generic IO decode ranges */ |
| 55 | uint32_t gen1_dec; |
| 56 | uint32_t gen2_dec; |
| 57 | uint32_t gen3_dec; |
| 58 | uint32_t gen4_dec; |
| 59 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 60 | /* Enable S0iX support */ |
Felix Singer | 743242b | 2023-06-16 01:33:25 +0200 | [diff] [blame] | 61 | bool s0ix_enable; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 62 | |
Duncan Laurie | 7fce30c | 2015-09-04 13:53:14 -0700 | [diff] [blame] | 63 | /* Enable DPTF support */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 64 | bool dptf_enable; |
Duncan Laurie | 7fce30c | 2015-09-04 13:53:14 -0700 | [diff] [blame] | 65 | |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 66 | /* Deep SX enables */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 67 | bool deep_s3_enable_ac; |
| 68 | bool deep_s3_enable_dc; |
| 69 | bool deep_s5_enable_ac; |
| 70 | bool deep_s5_enable_dc; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 71 | |
Duncan Laurie | edf1cb7 | 2015-07-24 15:37:13 -0700 | [diff] [blame] | 72 | /* |
| 73 | * Deep Sx Configuration |
| 74 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 75 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
Furquan Shaikh | a7104d0 | 2017-12-03 21:43:58 -0800 | [diff] [blame] | 76 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin |
Duncan Laurie | edf1cb7 | 2015-07-24 15:37:13 -0700 | [diff] [blame] | 77 | */ |
| 78 | uint32_t deep_sx_config; |
| 79 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 80 | /* TCC activation offset */ |
Angel Pons | 643c82e | 2020-09-24 16:43:21 +0200 | [diff] [blame] | 81 | uint32_t tcc_offset; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 82 | |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 83 | /* |
| 84 | * System Agent dynamic frequency configuration |
| 85 | * When enabled memory will be trained at two different frequencies. |
| 86 | * 0 = Disabled |
| 87 | * 1 = FixedLow |
| 88 | * 2 = FixedHigh |
| 89 | * 3 = Enabled |
| 90 | */ |
Praveen hodagatta pranesh | f7fdc3a | 2018-12-19 19:19:24 +0800 | [diff] [blame] | 91 | enum { |
| 92 | SaGv_Disabled, |
| 93 | SaGv_FixedLow, |
| 94 | SaGv_FixedHigh, |
| 95 | SaGv_Enabled, |
| 96 | } SaGv; |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 97 | |
| 98 | /* Enable/disable Rank Margin Tool */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 99 | bool RMT; |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 100 | |
Shaunak Saha | ef250c4 | 2018-08-31 12:49:08 -0700 | [diff] [blame] | 101 | /* Disable Command TriState */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 102 | bool CmdTriStateDis; |
Shaunak Saha | ef250c4 | 2018-08-31 12:49:08 -0700 | [diff] [blame] | 103 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 104 | /* Lan */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 105 | bool EnableLanLtr; |
| 106 | bool EnableLanK1Off; |
| 107 | bool LanClkReqSupported; |
Duncan Laurie | 14485ef | 2017-12-13 13:58:35 -0800 | [diff] [blame] | 108 | u8 LanClkReqNumber; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 109 | |
| 110 | /* SATA related */ |
Nico Huber | efc0fa0 | 2017-07-25 12:12:29 +0200 | [diff] [blame] | 111 | enum { |
Felix Singer | d60abfc | 2020-12-06 11:51:10 +0100 | [diff] [blame] | 112 | SATA_AHCI = 0, |
| 113 | SATA_RAID = 1, |
Nico Huber | efc0fa0 | 2017-07-25 12:12:29 +0200 | [diff] [blame] | 114 | } SataMode; |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 115 | bool SataSalpSupport; |
| 116 | bool SataPortsEnable[8]; |
| 117 | bool SataPortsDevSlp[8]; |
| 118 | bool SataPortsSpinUp[8]; |
| 119 | bool SataPortsHotPlug[8]; |
Matt DeVillier | 9e0d69b | 2017-10-10 14:03:36 -0500 | [diff] [blame] | 120 | u8 SataSpeedLimit; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 121 | |
| 122 | /* Audio related */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 123 | bool DspEnable; |
Duncan Laurie | 0c66e86 | 2015-09-03 16:05:59 -0700 | [diff] [blame] | 124 | |
Michael Niewöhner | 6238563 | 2019-09-23 14:38:41 +0200 | [diff] [blame] | 125 | /* HDA Virtual Channel Type Select */ |
| 126 | enum { |
| 127 | Vc0, |
| 128 | Vc1, |
| 129 | } PchHdaVcType; |
| 130 | |
Duncan Laurie | 0c66e86 | 2015-09-03 16:05:59 -0700 | [diff] [blame] | 131 | /* |
| 132 | * I/O Buffer Ownership: |
| 133 | * 0: HD-A Link |
| 134 | * 1 Shared, HD-A Link and I2S Port |
| 135 | * 3: I2S Ports |
| 136 | */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 137 | u8 IoBufferOwnership; |
| 138 | |
| 139 | /* Trace Hub function */ |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 140 | u32 TraceHubMemReg0Size; |
| 141 | u32 TraceHubMemReg1Size; |
| 142 | |
| 143 | /* DCI Enable/Disable */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 144 | bool PchDciEn; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 145 | |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 146 | /* |
Elyes HAOUAS | 79ccc69 | 2020-02-24 13:43:39 +0100 | [diff] [blame] | 147 | * PCIe Root Port configuration: |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 148 | * each element of array corresponds to |
| 149 | * respective PCIe root port. |
| 150 | */ |
| 151 | |
Maxim Polyakov | 0220d1e | 2019-03-18 17:38:44 +0300 | [diff] [blame] | 152 | /* PEG Max Link Width */ |
| 153 | enum { |
| 154 | Peg0_x16, |
| 155 | Peg0_x1, |
| 156 | Peg0_x2, |
| 157 | Peg0_x4, |
| 158 | Peg0_x8, |
| 159 | } Peg0MaxLinkWidth; |
| 160 | |
| 161 | enum { |
| 162 | Peg1_x8, |
| 163 | Peg1_x1, |
| 164 | Peg1_x2, |
| 165 | Peg1_x4, |
| 166 | } Peg1MaxLinkWidth; |
| 167 | |
| 168 | enum { |
| 169 | Peg2_x4, |
| 170 | Peg2_x1, |
| 171 | Peg2_x2, |
| 172 | } Peg2MaxLinkWidth; |
| 173 | |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 174 | /* |
| 175 | * Enable/Disable Root Port |
| 176 | * 0: Disable Root Port |
| 177 | * 1: Enable Root Port |
| 178 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 179 | bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 180 | |
| 181 | /* |
| 182 | * Enable/Disable Clk-req support for Root Port |
| 183 | * 0: Disable Clk-Req |
| 184 | * 1: Enable Clk-req |
| 185 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 186 | bool PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 187 | |
| 188 | /* |
| 189 | * Clk-req source for Root Port |
| 190 | */ |
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 191 | u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 192 | |
| 193 | /* |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 194 | * Clk source number for Root Port |
| 195 | */ |
| 196 | u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS]; |
| 197 | |
| 198 | /* |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 199 | * Enable/Disable AER (Advanced Error Reporting) for Root Port |
| 200 | * 0: Disable AER |
| 201 | * 1: Enable AER |
| 202 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 203 | bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 204 | |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 205 | /* |
| 206 | * Enable/Disable Latency Tolerance Reporting for Root Port |
| 207 | * 0: Disable LTR |
| 208 | * 1: Enable LTR |
| 209 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 210 | bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 211 | |
Duncan Laurie | 74ea48e | 2018-01-29 12:00:47 -0800 | [diff] [blame] | 212 | /* Enable/Disable HotPlug support for Root Port */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 213 | bool PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; |
Duncan Laurie | 74ea48e | 2018-01-29 12:00:47 -0800 | [diff] [blame] | 214 | |
Wim Vervoorn | d6b682c | 2020-05-07 12:41:13 +0200 | [diff] [blame] | 215 | /* PCIE RP Max Payload, Max Payload Size supported */ |
| 216 | enum { |
| 217 | RpMaxPayload_128, |
| 218 | RpMaxPayload_256, |
| 219 | } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; |
| 220 | |
Wim Vervoorn | 5819eab | 2020-05-07 13:16:32 +0200 | [diff] [blame] | 221 | /* PCIE RP ASPM, ASPM support for the root port */ |
| 222 | enum { |
| 223 | AspmDefault, |
| 224 | AspmDisabled, |
| 225 | AspmL0s, |
| 226 | AspmL1, |
| 227 | AspmL0sL1, |
| 228 | AspmAutoConfig, |
Benjamin Doron | b53858b | 2020-10-12 04:19:42 +0000 | [diff] [blame] | 229 | } pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS]; |
Wim Vervoorn | 5819eab | 2020-05-07 13:16:32 +0200 | [diff] [blame] | 230 | |
Benjamin Doron | adcb870 | 2020-03-14 01:53:25 +0000 | [diff] [blame] | 231 | /* PCIe RP L1 substate */ |
| 232 | enum { |
| 233 | L1SS_Default, |
| 234 | L1SS_Disabled, |
| 235 | L1SS_L1_1, |
| 236 | L1SS_L1_2, |
| 237 | } pcie_rp_l1substates[CONFIG_MAX_ROOT_PORTS]; |
| 238 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 239 | /* USB related */ |
Duncan Laurie | fe86666 | 2015-10-16 13:58:11 -0700 | [diff] [blame] | 240 | struct usb2_port_config usb2_ports[16]; |
| 241 | struct usb3_port_config usb3_ports[10]; |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 242 | bool SsicPortEnable; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 243 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 244 | /* |
| 245 | * SerialIO device mode selection: |
| 246 | * |
| 247 | * Device index: |
| 248 | * PchSerialIoIndexI2C0 |
| 249 | * PchSerialIoIndexI2C1 |
| 250 | * PchSerialIoIndexI2C2 |
| 251 | * PchSerialIoIndexI2C3 |
| 252 | * PchSerialIoIndexI2C4 |
| 253 | * PchSerialIoIndexI2C5 |
| 254 | * PchSerialIoIndexI2C6 |
| 255 | * PchSerialIoIndexSpi0 |
| 256 | * PchSerialIoIndexSpi1 |
| 257 | * PchSerialIoIndexUart0 |
| 258 | * PchSerialIoIndexUart1 |
| 259 | * PchSerialIoIndexUart2 |
| 260 | * |
| 261 | * Mode select: |
| 262 | * PchSerialIoDisabled |
| 263 | * PchSerialIoAcpi |
| 264 | * PchSerialIoPci |
| 265 | * PchSerialIoAcpiHidden |
| 266 | * PchSerialIoLegacyUart |
| 267 | */ |
| 268 | u8 SerialIoDevMode[PchSerialIoIndexMax]; |
| 269 | |
Duncan Laurie | c8d45ac | 2016-06-06 17:21:00 -0700 | [diff] [blame] | 270 | /* I2C */ |
Aaron Durbin | ed14a4e | 2016-11-09 17:04:15 -0600 | [diff] [blame] | 271 | /* Bus voltage level, default is 3.3V */ |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 272 | enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 273 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 274 | /* eMMC and SD */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 275 | bool ScsEmmcHs400Enabled; |
| 276 | bool EmmcHs400DllNeed; |
Pratik Prajapati | e072247 | 2018-08-22 18:58:38 -0700 | [diff] [blame] | 277 | u8 ScsEmmcHs400RxStrobeDll1; |
| 278 | u8 ScsEmmcHs400TxDataDll; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 279 | |
Maxim Polyakov | de08ae1 | 2019-03-21 18:50:42 +0300 | [diff] [blame] | 280 | enum { |
| 281 | Display_iGFX, |
| 282 | Display_PEG, |
| 283 | Display_PCH_PCIe, |
| 284 | Display_Auto, |
| 285 | Display_Switchable, |
| 286 | } PrimaryDisplay; |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 287 | bool SkipExtGfxScan; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 288 | |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 289 | /* GPIO IRQ Route The valid values is 14 or 15*/ |
| 290 | u8 GpioIrqSelect; |
| 291 | /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ |
| 292 | u8 SciIrqSelect; |
| 293 | /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/ |
| 294 | u8 TcoIrqSelect; |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 295 | bool TcoIrqEnable; |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 296 | /* Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.*/ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 297 | bool LockDownConfigGlobalSmi; |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 298 | /* |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 299 | * Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh |
Elyes HAOUAS | 59ab203 | 2021-01-16 14:55:58 +0100 | [diff] [blame] | 300 | * in the upper and lower 128-byte bank of RTC RAM. |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 301 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 302 | bool LockDownConfigRtcLock; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 303 | |
| 304 | /* |
| 305 | * Determine if WLAN wake from Sx, corresponds to the |
| 306 | * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. |
| 307 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 308 | bool PchPmWoWlanEnable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 309 | |
| 310 | /* |
| 311 | * Determine if WLAN wake from DeepSx, corresponds to |
| 312 | * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. |
| 313 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 314 | bool PchPmWoWlanDeepSxEnable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 315 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 316 | /* |
| 317 | * Corresponds to the "WOL Enable Override" bit in the General PM |
| 318 | * Configuration B (GEN_PMCON_B) register |
| 319 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 320 | bool WakeConfigWolEnableOverride; |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 321 | /* Determine if enable PCIe to wake from deep Sx*/ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 322 | bool WakeConfigPcieWakeFromDeepSx; |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 323 | /* Deep Sx Policy. Values 0: PchDeepSxPolDisable, |
| 324 | * 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn, |
| 325 | * 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn |
| 326 | */ |
| 327 | u8 PmConfigDeepSxPol; |
Nico Huber | 503965f | 2017-05-09 16:11:27 +0200 | [diff] [blame] | 328 | |
| 329 | enum { |
| 330 | SLP_S3_MIN_ASSERT_60US = 0, |
| 331 | SLP_S3_MIN_ASSERT_1MS = 1, |
| 332 | SLP_S3_MIN_ASSERT_50MS = 2, |
| 333 | SLP_S3_MIN_ASSERT_2S = 3, |
| 334 | } PmConfigSlpS3MinAssert; |
| 335 | |
| 336 | enum { |
| 337 | SLP_S4_MIN_ASSERT_PCH = 0, |
| 338 | SLP_S4_MIN_ASSERT_1S = 1, |
| 339 | SLP_S4_MIN_ASSERT_2S = 2, |
| 340 | SLP_S4_MIN_ASSERT_3S = 3, |
| 341 | SLP_S4_MIN_ASSERT_4S = 4, |
| 342 | } PmConfigSlpS4MinAssert; |
| 343 | |
| 344 | /* When deep Sx enabled: Must be greater than or equal to |
| 345 | all other minimum assertion widths. */ |
| 346 | enum { |
| 347 | SLP_SUS_MIN_ASSERT_0MS = 0, |
| 348 | SLP_SUS_MIN_ASSERT_500MS = 1, |
| 349 | SLP_SUS_MIN_ASSERT_1S = 2, |
| 350 | SLP_SUS_MIN_ASSERT_4S = 3, |
| 351 | } PmConfigSlpSusMinAssert; |
| 352 | |
| 353 | enum { |
| 354 | SLP_A_MIN_ASSERT_0MS = 0, |
| 355 | SLP_A_MIN_ASSERT_4S = 1, |
| 356 | SLP_A_MIN_ASSERT_98MS = 2, |
| 357 | SLP_A_MIN_ASSERT_2S = 3, |
| 358 | } PmConfigSlpAMinAssert; |
| 359 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 360 | /* |
Lee Leahy | b439a92 | 2017-03-16 16:44:36 -0700 | [diff] [blame] | 361 | * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, |
| 362 | * 1: Enabled |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 363 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 364 | bool PmConfigSlpStrchSusUp; |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 365 | /* |
| 366 | * PCH power button override period. |
| 367 | * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s |
| 368 | */ |
| 369 | u8 PmConfigPwrBtnOverridePeriod; |
Rizwan Qureshi | 0da186c | 2017-02-23 14:43:39 +0530 | [diff] [blame] | 370 | |
| 371 | /* |
| 372 | * PCH Pm Slp S0 Voltage Margining Enable |
| 373 | * Indicates platform supports VCCPrim_Core Voltage Margining |
| 374 | * in SLP_S0# asserted state. |
| 375 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 376 | bool PchPmSlpS0VmEnable; |
Rizwan Qureshi | 0da186c | 2017-02-23 14:43:39 +0530 | [diff] [blame] | 377 | |
Nico Huber | 503965f | 2017-05-09 16:11:27 +0200 | [diff] [blame] | 378 | enum { |
| 379 | RESET_POWER_CYCLE_DEFAULT = 0, |
| 380 | RESET_POWER_CYCLE_1S = 1, |
| 381 | RESET_POWER_CYCLE_2S = 2, |
| 382 | RESET_POWER_CYCLE_3S = 3, |
| 383 | RESET_POWER_CYCLE_4S = 4, |
| 384 | } PmConfigPwrCycDur; |
| 385 | |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 386 | enum serirq_mode serirq_mode; |
Nico Huber | 503965f | 2017-05-09 16:11:27 +0200 | [diff] [blame] | 387 | |
| 388 | enum { |
| 389 | SERIAL_IRQ_FRAME_PULSE_4CLK = 0, |
| 390 | SERIAL_IRQ_FRAME_PULSE_6CLK = 1, |
| 391 | SERIAL_IRQ_FRAME_PULSE_8CLK = 2, |
| 392 | } SerialIrqConfigStartFramePulse; |
| 393 | |
Subrata Banik | ce23d4c | 2018-06-04 10:05:07 +0530 | [diff] [blame] | 394 | /* |
Rizwan Qureshi | af31a99 | 2016-02-24 14:31:40 +0530 | [diff] [blame] | 395 | * VrConfig Settings for 5 domains |
Rizwan Qureshi | 2b1e8b3 | 2015-11-20 11:46:54 +0530 | [diff] [blame] | 396 | * 0 = System Agent, 1 = IA Core, 2 = Ring, |
| 397 | * 3 = GT unsliced, 4 = GT sliced |
| 398 | */ |
| 399 | struct vr_config domain_vr_config[NUM_VR_DOMAINS]; |
Michael Niewöhner | a64b4f4 | 2020-10-15 00:36:29 +0200 | [diff] [blame] | 400 | |
Rizwan Qureshi | af31a99 | 2016-02-24 14:31:40 +0530 | [diff] [blame] | 401 | /* |
| 402 | * Enable VR specific mailbox command |
Subrata Banik | 9a8b67d | 2016-04-20 14:19:53 +0530 | [diff] [blame] | 403 | * 000b - Don't Send any VR command |
| 404 | * 001b - VR command specifically for the MPS IMPV8 VR will be sent |
| 405 | * 010b - VR specific command sent for PS4 exit issue |
| 406 | * 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue |
Rizwan Qureshi | af31a99 | 2016-02-24 14:31:40 +0530 | [diff] [blame] | 407 | */ |
| 408 | u8 SendVrMbxCmd; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 409 | |
Rizwan Qureshi | ffe5810 | 2017-02-10 15:58:24 +0530 | [diff] [blame] | 410 | /* Enable/Disable host reads to PMC XRAM registers */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 411 | bool PchPmPmcReadDisable; |
Rizwan Qureshi | ffe5810 | 2017-02-10 15:58:24 +0530 | [diff] [blame] | 412 | |
Duncan Laurie | b25a45c | 2016-05-10 15:56:16 -0700 | [diff] [blame] | 413 | /* |
| 414 | * Use SD card detect GPIO with default config: |
| 415 | * - Edge triggered |
| 416 | * - No internal pull |
| 417 | * - Active both (high + low) |
| 418 | * - Can wake device from D3 |
| 419 | * - 100ms debounce timeout |
| 420 | * |
| 421 | * GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000, |
| 422 | * "\\_SB.PCI0.GPIO", 0, ResourceConsumer) |
Angel Pons | 6bd99f9 | 2021-02-20 00:16:47 +0100 | [diff] [blame] | 423 | * { sdcard_cd_gpio } |
Duncan Laurie | b25a45c | 2016-05-10 15:56:16 -0700 | [diff] [blame] | 424 | */ |
Angel Pons | 6bd99f9 | 2021-02-20 00:16:47 +0100 | [diff] [blame] | 425 | unsigned int sdcard_cd_gpio; |
Furquan Shaikh | 3bfe340 | 2016-10-18 14:25:25 -0700 | [diff] [blame] | 426 | |
| 427 | /* Wake Enable Bitmap for USB2 ports */ |
| 428 | u16 usb2_wake_enable_bitmap; |
| 429 | |
| 430 | /* Wake Enable Bitmap for USB3 ports */ |
| 431 | u8 usb3_wake_enable_bitmap; |
Duncan Laurie | b2aac85 | 2017-03-07 19:12:02 -0800 | [diff] [blame] | 432 | |
| 433 | /* |
| 434 | * Acoustic Noise Mitigation |
| 435 | * 0b - Disable |
| 436 | * 1b - Enable noise mitigation |
| 437 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 438 | bool AcousticNoiseMitigation; |
Duncan Laurie | b2aac85 | 2017-03-07 19:12:02 -0800 | [diff] [blame] | 439 | |
| 440 | /* |
| 441 | * Disable Fast Package C-state ramping |
| 442 | * Need to set AcousticNoiseMitigation = '1' first |
| 443 | * 0b - Enabled |
| 444 | * 1b - Disabled |
| 445 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 446 | bool FastPkgCRampDisableIa; |
| 447 | bool FastPkgCRampDisableGt; |
| 448 | bool FastPkgCRampDisableSa; |
Duncan Laurie | b2aac85 | 2017-03-07 19:12:02 -0800 | [diff] [blame] | 449 | |
| 450 | /* |
| 451 | * Adjust the VR slew rates |
| 452 | * Need to set AcousticNoiseMitigation = '1' first |
| 453 | * 000b - Fast/2 |
| 454 | * 001b - Fast/4 |
| 455 | * 010b - Fast/8 |
| 456 | * 011b - Fast/16 |
| 457 | */ |
| 458 | u8 SlowSlewRateForIa; |
| 459 | u8 SlowSlewRateForGt; |
| 460 | u8 SlowSlewRateForSa; |
Robbie Zhang | 7de0317 | 2017-02-21 14:00:31 -0800 | [diff] [blame] | 461 | |
Subrata Banik | 6b45ee4 | 2017-05-12 11:43:57 +0530 | [diff] [blame] | 462 | /* Enable/Disable EIST |
| 463 | * 1b - Enabled |
| 464 | * 0b - Disabled |
| 465 | */ |
Felix Singer | 552da56 | 2023-06-19 23:44:36 +0200 | [diff] [blame] | 466 | bool eist_enable; |
Rizwan Qureshi | b3e18c7 | 2017-09-25 17:35:15 +0530 | [diff] [blame] | 467 | |
| 468 | /* |
| 469 | * Activates VR mailbox command for Intersil VR C-state issues. |
| 470 | * 0 - no mailbox command sent. |
| 471 | * 1 - VR mailbox command sent for IA/GT rails only. |
| 472 | * 2 - VR mailbox command sent for IA/GT/SA rails. |
| 473 | */ |
| 474 | u8 IslVrCmd; |
Subrata Banik | 771d611 | 2017-11-29 16:17:13 +0530 | [diff] [blame] | 475 | |
Matt DeVillier | ddb4cf0 | 2020-03-27 14:13:07 -0500 | [diff] [blame] | 476 | /* i915 struct for GMA backlight control */ |
| 477 | struct i915_gpu_controller_info gfx; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 478 | }; |
| 479 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 480 | typedef struct soc_intel_skylake_config config_t; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 481 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 482 | #endif |