blob: 98e2413ee9648c5597d2645cebd7a4ae04b37b47 [file] [log] [blame]
Zheng Baob0f00ed2021-03-16 15:28:49 +08001/* SPDX-License-Identifier: GPL-2.0-only */
2
Zheng Baob0f00ed2021-03-16 15:28:49 +08003#include <amdblocks/i2c.h>
Kangheui Won62047e52021-04-15 17:34:09 +10004#include <console/console.h>
Zheng Baob0f00ed2021-03-16 15:28:49 +08005#include <soc/i2c.h>
6#include <soc/southbridge.h>
7#include "chip.h"
8
Fred Reitberger13831222022-10-17 11:49:55 -04009/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
10static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
11 I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
12 I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
13 I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
14 I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
15};
16
Zheng Baob0f00ed2021-03-16 15:28:49 +080017#if ENV_X86
18static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
19 { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
20 { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" },
21 { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" },
22 { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" }
23};
24#else
Kangheui Won62047e52021-04-15 17:34:09 +100025static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
Zheng Baob0f00ed2021-03-16 15:28:49 +080026 { I2C_MASTER_MODE, 0, "" },
27 { I2C_MASTER_MODE, 0, "" },
28 { I2C_MASTER_MODE, 0, "" },
29 { I2C_MASTER_MODE, 0, "" }
30};
31
32void i2c_set_bar(unsigned int bus, uintptr_t bar)
33{
34 if (bus >= ARRAY_SIZE(i2c_ctrlr)) {
Julius Wernere9665952022-01-21 17:06:20 -080035 printk(BIOS_ERR, "i2c index out of bounds: %u.", bus);
Zheng Baob0f00ed2021-03-16 15:28:49 +080036 return;
37 }
38
39 i2c_ctrlr[bus].bar = bar;
40}
41#endif
42
Fred Reitberger13831222022-10-17 11:49:55 -040043void reset_i2c_peripherals(void)
44{
45 const struct soc_amd_cezanne_config *cfg = config_of_soc();
46 struct soc_i2c_peripheral_reset_info reset_info;
47
48 reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
49 reset_info.i2c_scl = i2c_scl_pins;
50 reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
51 sb_reset_i2c_peripherals(&reset_info);
52}
53
Zheng Baob0f00ed2021-03-16 15:28:49 +080054void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
55{
Karthikeyan Ramasubramanianfec4db92021-06-02 16:14:39 -060056 const struct soc_amd_cezanne_config *config = config_of_soc();
Zheng Baob0f00ed2021-03-16 15:28:49 +080057
Felix Held556d1cc2022-02-02 22:11:52 +010058 if (bus >= ARRAY_SIZE(config->i2c_pad))
Karthikeyan Ramasubramanianfec4db92021-06-02 16:14:39 -060059 return;
60
Felix Held556d1cc2022-02-02 22:11:52 +010061 fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
Zheng Baob0f00ed2021-03-16 15:28:49 +080062}
63
64const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
65{
66 *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
67 return i2c_ctrlr;
68}
69
70const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
71{
72 const struct soc_amd_cezanne_config *config = config_of_soc();
73
74 *num_buses = ARRAY_SIZE(config->i2c);
75 return config->i2c;
76}