soc/amd/*/i2c: factor out common I2C pad configuration
The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO for future improvements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c
index 1fcab6a..bf47b81 100644
--- a/src/soc/amd/cezanne/i2c.c
+++ b/src/soc/amd/cezanne/i2c.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <amdblocks/acpimmio.h>
#include <amdblocks/i2c.h>
#include <console/console.h>
#include <soc/i2c.h>
@@ -36,24 +35,11 @@
void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
{
const struct soc_amd_cezanne_config *config = config_of_soc();
- uint32_t pad_ctrl;
- if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel))
+ if (bus >= ARRAY_SIZE(config->i2c_pad))
return;
- pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-
- pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
- pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
-
- pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
- pad_ctrl |= config->i2c_pad_ctrl_rx_sel[bus];
-
- pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
- pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
- I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
- pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
- misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
+ fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
}
const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)