Blame - src/mainboard/pcengines/apu2/Kconfig - coreboot

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Patrick Georgi	c49d7a3	2020-05-08 22:50:46 +0200	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	2
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	3	if BOARD_PCENGINES_APU2 \|\| BOARD_PCENGINES_APU3 \|\| BOARD_PCENGINES_APU4 \|\| \
				4	BOARD_PCENGINES_APU5
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	5
Elyes HAOUAS	f0c5be2	2018-11-27 20:36:44 +0100	[diff] [blame]	6	config BOARD_SPECIFIC_OPTIONS
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	7	def_bool y
				8	select CPU_AMD_PI_00730F01
				9	select NORTHBRIDGE_AMD_PI_00730F01
				10	select SOUTHBRIDGE_AMD_PI_AVALON
Kyösti Mälkki	657d68b	2019-12-03 12:36:09 +0200	[diff] [blame]	11	select DEFAULT_POST_ON_LPC
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	12	select SUPERIO_NUVOTON_NCT5104D
				13	select HAVE_PIRQ_TABLE
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	14	select HAVE_ACPI_TABLES
Felix Held	1f9f19b	2024-01-10 21:54:57 +0100	[diff] [blame]	15	select HUDSON_FADT_LEGACY_DEVICES
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	16	select BOARD_ROMSIZE_KB_8192
Michael Niewöhner	87cc889	2020-09-07 14:26:09 +0200	[diff] [blame]	17	select HAVE_SPD_IN_CBFS
Jes B. Klinke	c6b041a1	2022-04-19 14:00:33 -0700	[diff] [blame]	18	select MEMORY_MAPPED_TPM
Michał Żygowski	54fcb78	2018-08-03 18:23:52 +0200	[diff] [blame]	19	select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
Michał Żygowski	8e46d42	2020-03-20 16:19:55 +0100	[diff] [blame]	20	select PCIEXP_ASPM
				21	select PCIEXP_CLK_PM
				22	select PCIEXP_COMMON_CLOCK
				23	select PCIEXP_L1_SUB_STATE
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	24
				25	config MAINBOARD_DIR
Patrick Georgi	0bb8346	2019-11-22 20:58:58 +0100	[diff] [blame]	26	default "pcengines/apu2"
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	27
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	28	config VARIANT_DIR
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	29	default "apu2" if BOARD_PCENGINES_APU2
				30	default "apu3" if BOARD_PCENGINES_APU3
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	31	default "apu4" if BOARD_PCENGINES_APU4
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	32	default "apu5" if BOARD_PCENGINES_APU5
				33
				34	config DEVICETREE
Patrick Georgi	b8fba86	2020-06-17 21:06:53 +0200	[diff] [blame]	35	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	36
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	37	config MAINBOARD_PART_NUMBER
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	38	default "apu2" if BOARD_PCENGINES_APU2
				39	default "apu3" if BOARD_PCENGINES_APU3
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	40	default "apu4" if BOARD_PCENGINES_APU4
Kamil Wcislo	70b9245	2017-10-12 11:55:16 +0200	[diff] [blame]	41	default "apu5" if BOARD_PCENGINES_APU5
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	42
				43	config MAX_CPUS
				44	int
				45	default 4
				46
				47	config IRQ_SLOT_COUNT
				48	int
				49	default 11
				50
				51	config ONBOARD_VGA_IS_PRIMARY
				52	bool
				53	default y
				54
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	55	config AGESA_BINARY_PI_FILE
				56	string
				57	default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
				58
				59	choice
				60	prompt "J19 pins 1-10"
Michał Żygowski	cc16ec1	2018-09-24 13:17:40 +0200	[diff] [blame]	61	default APU2_PINMUX_UART_C
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	62
				63	config APU2_PINMUX_OFF_C
				64	bool "disable"
				65
				66	config APU2_PINMUX_GPIO0
				67	bool "GPIO"
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	68	depends on BOARD_PCENGINES_APU2 \|\| BOARD_PCENGINES_APU3 \|\| \
				69	BOARD_PCENGINES_APU4
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	70
				71	config APU2_PINMUX_UART_C
				72	bool "UART 0x3e8"
				73
				74	endchoice
				75
				76	choice
				77	prompt "J19 pins 11-20"
Michał Żygowski	cc16ec1	2018-09-24 13:17:40 +0200	[diff] [blame]	78	default APU2_PINMUX_UART_D
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	79
				80	config APU2_PINMUX_OFF_D
				81	bool "disable"
				82
				83	config APU2_PINMUX_GPIO1
				84	bool "GPIO"
Piotr Król	83b4fb9	2017-11-29 16:34:44 +0100	[diff] [blame]	85	depends on BOARD_PCENGINES_APU2 \|\| BOARD_PCENGINES_APU3 \|\| \
				86	BOARD_PCENGINES_APU4
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	87
				88	config APU2_PINMUX_UART_D
				89	bool "UART 0x2e8"
				90
				91	endchoice
				92
Patrick Georgi	44a46a1	2017-01-28 13:12:09 +0100	[diff] [blame]	93	config DIMM_SPD_SIZE
Patrick Georgi	44a46a1	2017-01-28 13:12:09 +0100	[diff] [blame]	94	default 128
				95
Piotr Kleinschmidt	7354605	2019-10-09 11:47:03 +0200	[diff] [blame]	96	config AGESA_USE_1_0_0_4_HEADER
				97	bool
				98	default y
				99	help
				100	Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is
				101	impossible to use the newest blob. Using an older 1.0.0.4 blob
				102	workarounds the problem, however some headers changes between blob
				103	revisions. This option removes the changes in headers introduced
				104	with AGESA 1.0.0.A to fit the 1.0.0.4 revision.
				105
Piotr Król	dcd2f17	2016-05-27 12:04:13 +0200	[diff] [blame]	106	endif # BOARD_PCENGINES_APU2