| # SPDX-License-Identifier: GPL-2.0-only |
| |
| if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ |
| BOARD_PCENGINES_APU5 |
| |
| config BOARD_SPECIFIC_OPTIONS |
| def_bool y |
| select CPU_AMD_PI_00730F01 |
| select NORTHBRIDGE_AMD_PI_00730F01 |
| select SOUTHBRIDGE_AMD_PI_AVALON |
| select DEFAULT_POST_ON_LPC |
| select SUPERIO_NUVOTON_NCT5104D |
| select HAVE_PIRQ_TABLE |
| select HAVE_ACPI_TABLES |
| select HUDSON_FADT_LEGACY_DEVICES |
| select BOARD_ROMSIZE_KB_8192 |
| select HAVE_SPD_IN_CBFS |
| select MEMORY_MAPPED_TPM |
| select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS |
| select PCIEXP_ASPM |
| select PCIEXP_CLK_PM |
| select PCIEXP_COMMON_CLOCK |
| select PCIEXP_L1_SUB_STATE |
| |
| config MAINBOARD_DIR |
| default "pcengines/apu2" |
| |
| config VARIANT_DIR |
| default "apu2" if BOARD_PCENGINES_APU2 |
| default "apu3" if BOARD_PCENGINES_APU3 |
| default "apu4" if BOARD_PCENGINES_APU4 |
| default "apu5" if BOARD_PCENGINES_APU5 |
| |
| config DEVICETREE |
| default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" |
| |
| config MAINBOARD_PART_NUMBER |
| default "apu2" if BOARD_PCENGINES_APU2 |
| default "apu3" if BOARD_PCENGINES_APU3 |
| default "apu4" if BOARD_PCENGINES_APU4 |
| default "apu5" if BOARD_PCENGINES_APU5 |
| |
| config MAX_CPUS |
| int |
| default 4 |
| |
| config IRQ_SLOT_COUNT |
| int |
| default 11 |
| |
| config ONBOARD_VGA_IS_PRIMARY |
| bool |
| default y |
| |
| config AGESA_BINARY_PI_FILE |
| string |
| default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin" |
| |
| choice |
| prompt "J19 pins 1-10" |
| default APU2_PINMUX_UART_C |
| |
| config APU2_PINMUX_OFF_C |
| bool "disable" |
| |
| config APU2_PINMUX_GPIO0 |
| bool "GPIO" |
| depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ |
| BOARD_PCENGINES_APU4 |
| |
| config APU2_PINMUX_UART_C |
| bool "UART 0x3e8" |
| |
| endchoice |
| |
| choice |
| prompt "J19 pins 11-20" |
| default APU2_PINMUX_UART_D |
| |
| config APU2_PINMUX_OFF_D |
| bool "disable" |
| |
| config APU2_PINMUX_GPIO1 |
| bool "GPIO" |
| depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ |
| BOARD_PCENGINES_APU4 |
| |
| config APU2_PINMUX_UART_D |
| bool "UART 0x2e8" |
| |
| endchoice |
| |
| config DIMM_SPD_SIZE |
| default 128 |
| |
| config AGESA_USE_1_0_0_4_HEADER |
| bool |
| default y |
| help |
| Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is |
| impossible to use the newest blob. Using an older 1.0.0.4 blob |
| workarounds the problem, however some headers changes between blob |
| revisions. This option removes the changes in headers introduced |
| with AGESA 1.0.0.A to fit the 1.0.0.4 revision. |
| |
| endif # BOARD_PCENGINES_APU2 |