Jamie Ryu | 0e7a52a | 2022-07-22 10:13:45 -0700 | [diff] [blame] | 1 | chip soc/intel/meteorlake |
| 2 | |
Harsha B R | ec0a85b | 2022-12-16 12:30:28 +0530 | [diff] [blame] | 3 | # GPE configuration |
| 4 | register "pmc_gpe0_dw0" = "GPP_B" |
| 5 | register "pmc_gpe0_dw1" = "GPP_D" |
| 6 | register "pmc_gpe0_dw2" = "GPP_E" |
| 7 | |
Jamie Ryu | 071d7f3 | 2022-07-22 12:29:57 -0700 | [diff] [blame] | 8 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 9 | register "gen1_dec" = "0x00fc0801" |
| 10 | register "gen2_dec" = "0x000c0201" |
| 11 | # EC memory map range is 0x900-0x9ff |
| 12 | register "gen3_dec" = "0x00fc0901" |
| 13 | |
Harsha B R | 7fb5bf8 | 2022-12-16 12:47:55 +0530 | [diff] [blame^] | 14 | register "serial_io_uart_mode" = "{ |
| 15 | [PchSerialIoIndexUART0] = PchSerialIoPci, |
| 16 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 17 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 18 | }" |
| 19 | |
Jamie Ryu | 0e7a52a | 2022-07-22 10:13:45 -0700 | [diff] [blame] | 20 | device domain 0 on |
| 21 | device ref igpu on end |
Harsha B R | a256bd6 | 2022-11-09 19:47:40 +0530 | [diff] [blame] | 22 | device ref heci1 on end |
| 23 | device ref tbt_pcie_rp0 on end |
| 24 | device ref tbt_pcie_rp1 on end |
| 25 | device ref tbt_pcie_rp2 on end |
| 26 | device ref tbt_pcie_rp3 on end |
| 27 | device ref tcss_xhci on end |
| 28 | device ref tcss_dma0 on end |
| 29 | device ref tcss_dma1 on end |
| 30 | device ref pcie_rp10 on |
| 31 | # Enable SSD Gen4 PCIE 10 using CLK 8 |
| 32 | register "pcie_rp[PCIE_RP(10)]" = "{ |
| 33 | .clk_src = 8, |
| 34 | .clk_req = 8, |
| 35 | .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, |
| 36 | }" |
| 37 | end # PCIE10 SSD Gen4 |
| 38 | device ref pcie_rp11 on |
| 39 | # Enable SSD Gen4 PCIE 11 using CLK 7 |
| 40 | register "pcie_rp[PCIE_RP(11)]" = "{ |
| 41 | .clk_src = 7, |
| 42 | .clk_req = 7, |
| 43 | .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, |
| 44 | }" |
| 45 | end # PCIE11 SSD Gen4 |
| 46 | device ref xhci on end |
| 47 | device ref i2c0 on end |
| 48 | device ref i2c1 on end |
| 49 | device ref i2c2 on end |
| 50 | device ref i2c3 on end |
| 51 | device ref i2c4 on end |
| 52 | device ref i2c5 on end |
| 53 | device ref shared_sram on end |
| 54 | device ref uart0 on end |
| 55 | device ref smbus on end |
Jamie Ryu | 0e7a52a | 2022-07-22 10:13:45 -0700 | [diff] [blame] | 56 | end |
| 57 | end |