blob: 8946b020d863a900d9a000be02389f5db1a0263e [file] [log] [blame]
Patrick Georgie72a8a32012-11-06 11:05:09 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 secunet Security Networks AG
5 * (Written by Nico Huber <nico.huber@secunet.com> for secunet)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Patrick Georgie72a8a32012-11-06 11:05:09 +010016 */
17
Kyösti Mälkki13f66502019-03-03 08:01:05 +020018#include <device/mmio.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020019#include <device/pci_ops.h>
Patrick Georgie72a8a32012-11-06 11:05:09 +010020#include <device/device.h>
21#include <device/pci.h>
22#include <device/pci_ids.h>
23
24#include "i82801ix.h"
25
26static void thermal_init(struct device *dev)
27{
Kyösti Mälkkic70eed12018-05-22 02:18:00 +030028 if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0)))
Patrick Georgie72a8a32012-11-06 11:05:09 +010029 return;
30
31 u8 reg8;
32 u32 reg32;
33
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080034 pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR);
Patrick Georgie72a8a32012-11-06 11:05:09 +010035 reg32 = pci_read_config32(dev, 0x04);
36 pci_write_config32(dev, 0x04, reg32 | (1 << 1));
37
38 write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */
39 write32(DEFAULT_TBAR + 0x44, 0);
40
41 write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */
42 write8(DEFAULT_TBAR + 0x41, 0xba);
43
44 reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */
45 write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7));
46 reg8 = read8(DEFAULT_TBAR + 0x48);
47 write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7));
48
49 reg32 = pci_read_config32(dev, 0x04);
50 pci_write_config32(dev, 0x04, reg32 & ~(1 << 1));
51 pci_write_config32(dev, 0x10, 0);
52}
53
Patrick Georgie72a8a32012-11-06 11:05:09 +010054static struct pci_operations thermal_pci_ops = {
Subrata Banik4a0f0712019-03-20 14:29:47 +053055 .set_subsystem = pci_dev_set_subsystem,
Patrick Georgie72a8a32012-11-06 11:05:09 +010056};
57
58static struct device_operations device_ops = {
59 .read_resources = pci_dev_read_resources,
60 .set_resources = pci_dev_set_resources,
61 .enable_resources = pci_dev_enable_resources,
62 .init = thermal_init,
63 .scan_bus = 0,
64 .ops_pci = &thermal_pci_ops,
65};
66
67static const struct pci_driver ich9_thermal __pci_driver = {
68 .ops = &device_ops,
69 .vendor = PCI_VENDOR_ID_INTEL,
Felix Singer7f8b0cd82019-11-10 11:04:08 +010070 .device = PCI_DEVICE_ID_INTEL_82801IB_THERMAL,
Patrick Georgie72a8a32012-11-06 11:05:09 +010071};