Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 9 | #include <delay.h> |
| 10 | #include <device/azalia_device.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 11 | #include "chip.h" |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 12 | #include "i82801jx.h" |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 13 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 14 | static int codec_detect(u8 *base) |
| 15 | { |
| 16 | u32 reg32; |
| 17 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 18 | /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ |
Angel Pons | 61dd836 | 2020-12-05 18:02:32 +0100 | [diff] [blame] | 19 | if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 20 | goto no_codec; |
| 21 | |
| 22 | /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ |
Angel Pons | 61dd836 | 2020-12-05 18:02:32 +0100 | [diff] [blame] | 23 | if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 24 | goto no_codec; |
| 25 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 26 | /* Read in Codec location (BAR + 0xe)[2..0] */ |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame] | 27 | reg32 = read32(base + HDA_STATESTS_REG); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 28 | reg32 &= 0x0f; |
| 29 | if (!reg32) |
| 30 | goto no_codec; |
| 31 | |
| 32 | return reg32; |
| 33 | |
| 34 | no_codec: |
| 35 | /* Codec Not found */ |
| 36 | /* Put HDA back in reset (BAR + 0x8) [0] */ |
Angel Pons | 61dd836 | 2020-12-05 18:02:32 +0100 | [diff] [blame] | 37 | azalia_set_bits(base + HDA_GCTL_REG, 1, 0); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 38 | printk(BIOS_DEBUG, "Azalia: No codec!\n"); |
| 39 | return 0; |
| 40 | } |
| 41 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 42 | /* |
| 43 | * Wait 50usec for the codec to indicate it is ready. |
| 44 | * No response would imply that the codec is non-operative. |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 45 | */ |
| 46 | |
| 47 | static int wait_for_ready(u8 *base) |
| 48 | { |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 49 | /* Use a 50 usec timeout - the Linux kernel uses the same duration */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 50 | int timeout = 50; |
| 51 | |
| 52 | while (timeout--) { |
| 53 | u32 reg32 = read32(base + HDA_ICII_REG); |
| 54 | if (!(reg32 & HDA_ICII_BUSY)) |
| 55 | return 0; |
| 56 | udelay(1); |
| 57 | } |
| 58 | |
| 59 | return -1; |
| 60 | } |
| 61 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 62 | /* |
| 63 | * Wait 50usec for the codec to indicate that it accepted the previous command. |
| 64 | * No response would imply that the code is non-operative. |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 65 | */ |
| 66 | |
| 67 | static int wait_for_valid(u8 *base) |
| 68 | { |
| 69 | u32 reg32; |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 70 | /* Use a 50 usec timeout - the Linux kernel uses the same duration */ |
| 71 | int timeout = 50; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 72 | |
| 73 | /* Send the verb to the codec */ |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame] | 74 | reg32 = read32(base + HDA_ICII_REG); |
| 75 | reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; |
| 76 | write32(base + HDA_ICII_REG, reg32); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 77 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 78 | while (timeout--) { |
| 79 | reg32 = read32(base + HDA_ICII_REG); |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 80 | if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 81 | return 0; |
| 82 | udelay(1); |
| 83 | } |
| 84 | |
| 85 | return -1; |
| 86 | } |
| 87 | |
| 88 | static void codec_init(struct device *dev, u8 *base, int addr) |
| 89 | { |
| 90 | u32 reg32; |
| 91 | const u32 *verb; |
| 92 | u32 verb_size; |
| 93 | int i; |
| 94 | |
Angel Pons | aaa8ab7 | 2020-06-21 15:33:24 +0200 | [diff] [blame] | 95 | printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 96 | |
| 97 | /* 1 */ |
Angel Pons | 554713e | 2020-10-24 23:23:07 +0200 | [diff] [blame] | 98 | if (wait_for_ready(base) < 0) { |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 99 | printk(BIOS_DEBUG, " codec not ready.\n"); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 100 | return; |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 101 | } |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 102 | |
| 103 | reg32 = (addr << 28) | 0x000f0000; |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame] | 104 | write32(base + HDA_IC_REG, reg32); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 105 | |
Angel Pons | 554713e | 2020-10-24 23:23:07 +0200 | [diff] [blame] | 106 | if (wait_for_valid(base) < 0) { |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 107 | printk(BIOS_DEBUG, " codec not valid.\n"); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 108 | return; |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 109 | } |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 110 | |
| 111 | /* 2 */ |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 112 | reg32 = read32(base + HDA_IR_REG); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 113 | printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); |
Angel Pons | d425ddd | 2020-12-05 18:22:58 +0100 | [diff] [blame] | 114 | verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 115 | |
| 116 | if (!verb_size) { |
| 117 | printk(BIOS_DEBUG, "Azalia: No verb!\n"); |
| 118 | return; |
| 119 | } |
| 120 | printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); |
| 121 | |
| 122 | /* 3 */ |
| 123 | for (i = 0; i < verb_size; i++) { |
Angel Pons | 554713e | 2020-10-24 23:23:07 +0200 | [diff] [blame] | 124 | if (wait_for_ready(base) < 0) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 125 | return; |
| 126 | |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame] | 127 | write32(base + HDA_IC_REG, verb[i]); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 128 | |
Angel Pons | 554713e | 2020-10-24 23:23:07 +0200 | [diff] [blame] | 129 | if (wait_for_valid(base) < 0) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 130 | return; |
| 131 | } |
| 132 | printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); |
| 133 | } |
| 134 | |
| 135 | static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) |
| 136 | { |
| 137 | int i; |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 138 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 139 | for (i = 2; i >= 0; i--) { |
| 140 | if (codec_mask & (1 << i)) |
| 141 | codec_init(dev, base, i); |
| 142 | } |
| 143 | |
| 144 | for (i = 0; i < pc_beep_verbs_size; i++) { |
Angel Pons | 554713e | 2020-10-24 23:23:07 +0200 | [diff] [blame] | 145 | if (wait_for_ready(base) < 0) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 146 | return; |
| 147 | |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame] | 148 | write32(base + HDA_IC_REG, pc_beep_verbs[i]); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 149 | |
Angel Pons | 554713e | 2020-10-24 23:23:07 +0200 | [diff] [blame] | 150 | if (wait_for_valid(base) < 0) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 151 | return; |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | static void azalia_init(struct device *dev) |
| 156 | { |
| 157 | u8 *base; |
| 158 | struct resource *res; |
| 159 | u32 codec_mask; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 160 | |
| 161 | // ESD |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 162 | pci_update_config32(dev, 0x134, ~0x00ff0000, 2 << 16); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 163 | |
| 164 | // Link1 description |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 165 | pci_update_config32(dev, 0x140, ~0x00ff0000, 2 << 16); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 166 | |
| 167 | // Port VC0 Resource Control Register |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 168 | pci_update_config32(dev, 0x114, ~0x000000ff, 1); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 169 | |
| 170 | // VCi traffic class |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 171 | pci_or_config8(dev, 0x44, 7 << 0); // TC7 |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 172 | |
| 173 | // VCi Resource Control |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 174 | pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 175 | |
| 176 | /* Set Bus Master */ |
Elyes HAOUAS | ca4ff25 | 2020-04-28 10:29:11 +0200 | [diff] [blame] | 177 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 178 | |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 179 | // Docking not supported |
| 180 | pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 181 | |
| 182 | /* Lock some R/WO bits by writing their current value. */ |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 183 | pci_update_config32(dev, 0x74, ~0, 0); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 184 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 185 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 186 | if (!res) |
| 187 | return; |
| 188 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 189 | // NOTE this will break as soon as the Azalia get's a bar above 4G. |
| 190 | // Is there anything we can do about it? |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 191 | base = res2mmio(res, 0, 0); |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 192 | printk(BIOS_DEBUG, "Azalia: base = %p\n", base); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 193 | codec_mask = codec_detect(base); |
| 194 | |
| 195 | if (codec_mask) { |
| 196 | printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); |
| 197 | codecs_init(dev, base, codec_mask); |
| 198 | } |
| 199 | } |
| 200 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 201 | static struct device_operations azalia_ops = { |
| 202 | .read_resources = pci_dev_read_resources, |
| 203 | .set_resources = pci_dev_set_resources, |
| 204 | .enable_resources = pci_dev_enable_resources, |
| 205 | .init = azalia_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 206 | .ops_pci = &pci_dev_ops_pci, |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 207 | }; |
| 208 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 209 | static const unsigned short pci_device_ids[] = { |
| 210 | 0x3a3e, |
| 211 | 0x3a6e, |
| 212 | 0 |
| 213 | }; |
| 214 | |
| 215 | static const struct pci_driver i82801jx_azalia __pci_driver = { |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 216 | .ops = &azalia_ops, |
| 217 | .vendor = PCI_VENDOR_ID_INTEL, |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 218 | .devices = pci_device_ids, |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 219 | }; |