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Angel Pons182dbde2020-04-02 23:49:05 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Arthur Heymans7b9c1392017-04-09 20:40:39 +02002
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_ids.h>
7#include <device/pci_ops.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02008#include <device/mmio.h>
Arthur Heymans7b9c1392017-04-09 20:40:39 +02009#include <delay.h>
10#include <device/azalia_device.h>
Kyösti Mälkki12b121c2019-08-18 16:33:39 +030011#include "chip.h"
Arthur Heymans349e0852017-04-09 20:48:37 +020012#include "i82801jx.h"
Arthur Heymans7b9c1392017-04-09 20:40:39 +020013
14#define HDA_ICII_REG 0x68
15#define HDA_ICII_BUSY (1 << 0)
16#define HDA_ICII_VALID (1 << 1)
17
Arthur Heymans349e0852017-04-09 20:48:37 +020018typedef struct southbridge_intel_i82801jx_config config_t;
Arthur Heymans7b9c1392017-04-09 20:40:39 +020019
20static int set_bits(void *port, u32 mask, u32 val)
21{
22 u32 reg32;
23 int count;
24
25 /* Write (val & mask) to port */
26 val &= mask;
27 reg32 = read32(port);
28 reg32 &= ~mask;
29 reg32 |= val;
30 write32(port, reg32);
31
32 /* Wait for readback of register to
33 * match what was just written to it
34 */
35 count = 50;
36 do {
37 /* Wait 1ms based on BKDG wait time */
38 mdelay(1);
39 reg32 = read32(port);
40 reg32 &= mask;
41 } while ((reg32 != val) && --count);
42
43 /* Timeout occurred */
44 if (!count)
45 return -1;
46 return 0;
47}
48
49static int codec_detect(u8 *base)
50{
51 u32 reg32;
52
53 /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
54 if (set_bits(base + 0x08, 1, 0) == -1)
55 goto no_codec;
56
57 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
58 if (set_bits(base + 0x08, 1, 1) == -1)
59 goto no_codec;
60
61 /* Read in Codec location (BAR + 0xe)[2..0]*/
62 reg32 = read32(base + 0xe);
63 reg32 &= 0x0f;
64 if (!reg32)
65 goto no_codec;
66
67 return reg32;
68
69no_codec:
70 /* Codec Not found */
71 /* Put HDA back in reset (BAR + 0x8) [0] */
72 set_bits(base + 0x08, 1, 0);
73 printk(BIOS_DEBUG, "Azalia: No codec!\n");
74 return 0;
75}
76
Elyes HAOUASe414a4e2019-01-03 10:40:43 +010077static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb)
Arthur Heymans7b9c1392017-04-09 20:40:39 +020078{
79 int idx=0;
80
81 while (idx < (cim_verb_data_size / sizeof(u32))) {
82 u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
83 if (cim_verb_data[idx] != viddid) {
84 idx += verb_size + 3; // skip verb + header
85 continue;
86 }
87 *verb = &cim_verb_data[idx+3];
88 return verb_size;
89 }
90
91 /* Not all codecs need to load another verb */
92 return 0;
93}
94
95/**
96 * Wait 50usec for the codec to indicate it is ready
97 * no response would imply that the codec is non-operative
98 */
99
100static int wait_for_ready(u8 *base)
101{
102 /* Use a 50 usec timeout - the Linux kernel uses the
103 * same duration */
104
105 int timeout = 50;
106
107 while (timeout--) {
108 u32 reg32 = read32(base + HDA_ICII_REG);
109 if (!(reg32 & HDA_ICII_BUSY))
110 return 0;
111 udelay(1);
112 }
113
114 return -1;
115}
116
117/**
118 * Wait 50usec for the codec to indicate that it accepted
119 * the previous command. No response would imply that the code
120 * is non-operative
121 */
122
123static int wait_for_valid(u8 *base)
124{
125 u32 reg32;
126
127 /* Send the verb to the codec */
128 reg32 = read32(base + 0x68);
129 reg32 |= (1 << 0) | (1 << 1);
130 write32(base + 0x68, reg32);
131
132 /* Use a 50 usec timeout - the Linux kernel uses the
133 * same duration */
134
135 int timeout = 50;
136 while (timeout--) {
137 reg32 = read32(base + HDA_ICII_REG);
138 if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
139 HDA_ICII_VALID)
140 return 0;
141 udelay(1);
142 }
143
144 return -1;
145}
146
147static void codec_init(struct device *dev, u8 *base, int addr)
148{
149 u32 reg32;
150 const u32 *verb;
151 u32 verb_size;
152 int i;
153
154 printk(BIOS_DEBUG, "HD Audio: Initializing codec #%d\n", addr);
155
156 /* 1 */
157 if (wait_for_ready(base) == -1)
158 return;
159
160 reg32 = (addr << 28) | 0x000f0000;
161 write32(base + 0x60, reg32);
162
163 if (wait_for_valid(base) == -1)
164 return;
165
166 reg32 = read32(base + 0x64);
167
168 /* 2 */
169 printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
170 verb_size = find_verb(dev, reg32, &verb);
171
172 if (!verb_size) {
173 printk(BIOS_DEBUG, "Azalia: No verb!\n");
174 return;
175 }
176 printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
177
178 /* 3 */
179 for (i = 0; i < verb_size; i++) {
180 if (wait_for_ready(base) == -1)
181 return;
182
183 write32(base + 0x60, verb[i]);
184
185 if (wait_for_valid(base) == -1)
186 return;
187 }
188 printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
189}
190
191static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
192{
193 int i;
194 for (i = 2; i >= 0; i--) {
195 if (codec_mask & (1 << i))
196 codec_init(dev, base, i);
197 }
198
199 for (i = 0; i < pc_beep_verbs_size; i++) {
200 if (wait_for_ready(base) == -1)
201 return;
202
203 write32(base + 0x60, pc_beep_verbs[i]);
204
205 if (wait_for_valid(base) == -1)
206 return;
207 }
208}
209
210static void azalia_init(struct device *dev)
211{
212 u8 *base;
213 struct resource *res;
214 u32 codec_mask;
215 u8 reg8;
216 u32 reg32;
217
218 // ESD
219 reg32 = pci_read_config32(dev, 0x134);
220 reg32 &= 0xff00ffff;
221 reg32 |= (2 << 16);
222 pci_write_config32(dev, 0x134, reg32);
223
224 // Link1 description
225 reg32 = pci_read_config32(dev, 0x140);
226 reg32 &= 0xff00ffff;
227 reg32 |= (2 << 16);
228 pci_write_config32(dev, 0x140, reg32);
229
230 // Port VC0 Resource Control Register
231 reg32 = pci_read_config32(dev, 0x114);
232 reg32 &= 0xffffff00;
233 reg32 |= 1;
234 pci_write_config32(dev, 0x114, reg32);
235
236 // VCi traffic class
237 reg8 = pci_read_config8(dev, 0x44);
238 reg8 |= (7 << 0); // TC7
239 pci_write_config8(dev, 0x44, reg8);
240
241 // VCi Resource Control
242 reg32 = pci_read_config32(dev, 0x120);
243 reg32 |= (1 << 31);
244 reg32 |= (1 << 24); // VCi ID
245 reg32 |= (0x80 << 0); // VCi map
246 pci_write_config32(dev, 0x120, reg32);
247
248 /* Set Bus Master */
Elyes HAOUASca4ff252020-04-28 10:29:11 +0200249 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
Arthur Heymans7b9c1392017-04-09 20:40:39 +0200250
251 reg8 = pci_read_config8(dev, 0x4d); // Docking Status
252 reg8 &= ~(1 << 7); // Docking not supported
253 pci_write_config8(dev, 0x4d, reg8);
254
255 /* Lock some R/WO bits by writing their current value. */
256 reg32 = pci_read_config32(dev, 0x74);
257 pci_write_config32(dev, 0x74, reg32);
258
259 res = find_resource(dev, 0x10);
260 if (!res)
261 return;
262
263 // NOTE this will break as soon as the Azalia get's a bar above
264 // 4G. Is there anything we can do about it?
265 base = res2mmio(res, 0, 0);
266 printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
267 codec_mask = codec_detect(base);
268
269 if (codec_mask) {
270 printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
271 codecs_init(dev, base, codec_mask);
272 }
273}
274
Arthur Heymans7b9c1392017-04-09 20:40:39 +0200275static struct device_operations azalia_ops = {
276 .read_resources = pci_dev_read_resources,
277 .set_resources = pci_dev_set_resources,
278 .enable_resources = pci_dev_enable_resources,
279 .init = azalia_init,
Angel Pons1fc0edd2020-05-31 00:03:28 +0200280 .ops_pci = &pci_dev_ops_pci,
Arthur Heymans7b9c1392017-04-09 20:40:39 +0200281};
282
Arthur Heymans349e0852017-04-09 20:48:37 +0200283static const unsigned short pci_device_ids[] = {
284 0x3a3e,
285 0x3a6e,
286 0
287};
288
289static const struct pci_driver i82801jx_azalia __pci_driver = {
Arthur Heymans7b9c1392017-04-09 20:40:39 +0200290 .ops = &azalia_ops,
291 .vendor = PCI_VENDOR_ID_INTEL,
Arthur Heymans349e0852017-04-09 20:48:37 +0200292 .devices = pci_device_ids,
Arthur Heymans7b9c1392017-04-09 20:40:39 +0200293};