Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 9 | #include <delay.h> |
| 10 | #include <device/azalia_device.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 11 | #include "chip.h" |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 12 | #include "i82801jx.h" |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 13 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 14 | static int set_bits(void *port, u32 mask, u32 val) |
| 15 | { |
| 16 | u32 reg32; |
| 17 | int count; |
| 18 | |
| 19 | /* Write (val & mask) to port */ |
| 20 | val &= mask; |
| 21 | reg32 = read32(port); |
| 22 | reg32 &= ~mask; |
| 23 | reg32 |= val; |
| 24 | write32(port, reg32); |
| 25 | |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 26 | /* Wait for readback of register to match what was just written to it */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 27 | count = 50; |
| 28 | do { |
| 29 | /* Wait 1ms based on BKDG wait time */ |
| 30 | mdelay(1); |
| 31 | reg32 = read32(port); |
| 32 | reg32 &= mask; |
| 33 | } while ((reg32 != val) && --count); |
| 34 | |
| 35 | /* Timeout occurred */ |
| 36 | if (!count) |
| 37 | return -1; |
| 38 | return 0; |
| 39 | } |
| 40 | |
| 41 | static int codec_detect(u8 *base) |
| 42 | { |
| 43 | u32 reg32; |
| 44 | |
| 45 | /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 46 | if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 47 | goto no_codec; |
| 48 | |
| 49 | /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 50 | if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 51 | goto no_codec; |
| 52 | |
| 53 | /* Read in Codec location (BAR + 0xe)[2..0]*/ |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 54 | reg32 = read32(base + HDA_STATESTS_REG); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 55 | reg32 &= 0x0f; |
| 56 | if (!reg32) |
| 57 | goto no_codec; |
| 58 | |
| 59 | return reg32; |
| 60 | |
| 61 | no_codec: |
| 62 | /* Codec Not found */ |
| 63 | /* Put HDA back in reset (BAR + 0x8) [0] */ |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 64 | set_bits(base + HDA_GCTL_REG, 1, 0); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "Azalia: No codec!\n"); |
| 66 | return 0; |
| 67 | } |
| 68 | |
Elyes HAOUAS | e414a4e | 2019-01-03 10:40:43 +0100 | [diff] [blame] | 69 | static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 70 | { |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 71 | int idx = 0; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 72 | |
| 73 | while (idx < (cim_verb_data_size / sizeof(u32))) { |
| 74 | u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 |
| 75 | if (cim_verb_data[idx] != viddid) { |
| 76 | idx += verb_size + 3; // skip verb + header |
| 77 | continue; |
| 78 | } |
| 79 | *verb = &cim_verb_data[idx+3]; |
| 80 | return verb_size; |
| 81 | } |
| 82 | |
| 83 | /* Not all codecs need to load another verb */ |
| 84 | return 0; |
| 85 | } |
| 86 | |
| 87 | /** |
| 88 | * Wait 50usec for the codec to indicate it is ready |
| 89 | * no response would imply that the codec is non-operative |
| 90 | */ |
| 91 | |
| 92 | static int wait_for_ready(u8 *base) |
| 93 | { |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 94 | /* Use a 50 usec timeout - the Linux kernel uses the same duration */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 95 | int timeout = 50; |
| 96 | |
| 97 | while (timeout--) { |
| 98 | u32 reg32 = read32(base + HDA_ICII_REG); |
| 99 | if (!(reg32 & HDA_ICII_BUSY)) |
| 100 | return 0; |
| 101 | udelay(1); |
| 102 | } |
| 103 | |
| 104 | return -1; |
| 105 | } |
| 106 | |
| 107 | /** |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 108 | * Wait 50usec for the codec to indicate that it accepted the previous command. |
| 109 | * No response would imply that the code is non-operative. |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 110 | */ |
| 111 | |
| 112 | static int wait_for_valid(u8 *base) |
| 113 | { |
| 114 | u32 reg32; |
| 115 | |
| 116 | /* Send the verb to the codec */ |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 117 | reg32 = read32(base + HDA_ICII_REG); |
| 118 | reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; |
| 119 | write32(base + HDA_ICII_REG, reg32); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 120 | |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 121 | /* Use a 50 usec timeout - the Linux kernel uses the same duration */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 122 | |
| 123 | int timeout = 50; |
| 124 | while (timeout--) { |
| 125 | reg32 = read32(base + HDA_ICII_REG); |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 126 | if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 127 | return 0; |
| 128 | udelay(1); |
| 129 | } |
| 130 | |
| 131 | return -1; |
| 132 | } |
| 133 | |
| 134 | static void codec_init(struct device *dev, u8 *base, int addr) |
| 135 | { |
| 136 | u32 reg32; |
| 137 | const u32 *verb; |
| 138 | u32 verb_size; |
| 139 | int i; |
| 140 | |
Angel Pons | aaa8ab7 | 2020-06-21 15:33:24 +0200 | [diff] [blame] | 141 | printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 142 | |
| 143 | /* 1 */ |
| 144 | if (wait_for_ready(base) == -1) |
| 145 | return; |
| 146 | |
| 147 | reg32 = (addr << 28) | 0x000f0000; |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 148 | write32(base + HDA_IC_REG, reg32); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 149 | |
| 150 | if (wait_for_valid(base) == -1) |
| 151 | return; |
| 152 | |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 153 | reg32 = read32(base + HDA_IR_REG); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 154 | |
| 155 | /* 2 */ |
| 156 | printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); |
| 157 | verb_size = find_verb(dev, reg32, &verb); |
| 158 | |
| 159 | if (!verb_size) { |
| 160 | printk(BIOS_DEBUG, "Azalia: No verb!\n"); |
| 161 | return; |
| 162 | } |
| 163 | printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); |
| 164 | |
| 165 | /* 3 */ |
| 166 | for (i = 0; i < verb_size; i++) { |
| 167 | if (wait_for_ready(base) == -1) |
| 168 | return; |
| 169 | |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 170 | write32(base + HDA_IC_REG, verb[i]); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 171 | |
| 172 | if (wait_for_valid(base) == -1) |
| 173 | return; |
| 174 | } |
| 175 | printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); |
| 176 | } |
| 177 | |
| 178 | static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) |
| 179 | { |
| 180 | int i; |
| 181 | for (i = 2; i >= 0; i--) { |
| 182 | if (codec_mask & (1 << i)) |
| 183 | codec_init(dev, base, i); |
| 184 | } |
| 185 | |
| 186 | for (i = 0; i < pc_beep_verbs_size; i++) { |
| 187 | if (wait_for_ready(base) == -1) |
| 188 | return; |
| 189 | |
Elyes HAOUAS | 388c88b | 2020-08-03 15:36:20 +0200 | [diff] [blame^] | 190 | write32(base + HDA_IC_REG, pc_beep_verbs[i]); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 191 | |
| 192 | if (wait_for_valid(base) == -1) |
| 193 | return; |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | static void azalia_init(struct device *dev) |
| 198 | { |
| 199 | u8 *base; |
| 200 | struct resource *res; |
| 201 | u32 codec_mask; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 202 | |
| 203 | // ESD |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 204 | pci_update_config32(dev, 0x134, ~0x00ff0000, 2 << 16); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 205 | |
| 206 | // Link1 description |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 207 | pci_update_config32(dev, 0x140, ~0x00ff0000, 2 << 16); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 208 | |
| 209 | // Port VC0 Resource Control Register |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 210 | pci_update_config32(dev, 0x114, ~0x000000ff, 1); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 211 | |
| 212 | // VCi traffic class |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 213 | pci_or_config8(dev, 0x44, 7 << 0); // TC7 |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 214 | |
| 215 | // VCi Resource Control |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 216 | pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 217 | |
| 218 | /* Set Bus Master */ |
Elyes HAOUAS | ca4ff25 | 2020-04-28 10:29:11 +0200 | [diff] [blame] | 219 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 220 | |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 221 | // Docking not supported |
| 222 | pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 223 | |
| 224 | /* Lock some R/WO bits by writing their current value. */ |
Angel Pons | 2048cb4 | 2020-06-08 02:09:33 +0200 | [diff] [blame] | 225 | pci_update_config32(dev, 0x74, ~0, 0); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 226 | |
| 227 | res = find_resource(dev, 0x10); |
| 228 | if (!res) |
| 229 | return; |
| 230 | |
| 231 | // NOTE this will break as soon as the Azalia get's a bar above |
| 232 | // 4G. Is there anything we can do about it? |
| 233 | base = res2mmio(res, 0, 0); |
Angel Pons | 7a2864b | 2020-06-21 13:29:28 +0200 | [diff] [blame] | 234 | printk(BIOS_DEBUG, "Azalia: base = %p\n", base); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 235 | codec_mask = codec_detect(base); |
| 236 | |
| 237 | if (codec_mask) { |
| 238 | printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); |
| 239 | codecs_init(dev, base, codec_mask); |
| 240 | } |
| 241 | } |
| 242 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 243 | static struct device_operations azalia_ops = { |
| 244 | .read_resources = pci_dev_read_resources, |
| 245 | .set_resources = pci_dev_set_resources, |
| 246 | .enable_resources = pci_dev_enable_resources, |
| 247 | .init = azalia_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 248 | .ops_pci = &pci_dev_ops_pci, |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 249 | }; |
| 250 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 251 | static const unsigned short pci_device_ids[] = { |
| 252 | 0x3a3e, |
| 253 | 0x3a6e, |
| 254 | 0 |
| 255 | }; |
| 256 | |
| 257 | static const struct pci_driver i82801jx_azalia __pci_driver = { |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 258 | .ops = &azalia_ops, |
| 259 | .vendor = PCI_VENDOR_ID_INTEL, |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 260 | .devices = pci_device_ids, |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 261 | }; |