Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * Copyright (C) 2013 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <stdint.h> |
| 19 | #include <stdlib.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 23 | #include <device/pci_def.h> |
| 24 | #include <elog.h> |
| 25 | #include <cpu/x86/msr.h> |
| 26 | #include <cpu/intel/speedstep.h> |
| 27 | #include <cpu/intel/turbo.h> |
| 28 | #include <arch/cpu.h> |
| 29 | |
| 30 | #include "nehalem.h" |
| 31 | |
| 32 | static void nehalem_setup_bars(void) |
| 33 | { |
| 34 | /* Setting up Southbridge. In the northbridge code. */ |
| 35 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 36 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 37 | |
| 38 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 39 | /* Enable ACPI BAR */ |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 40 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 41 | |
| 42 | printk(BIOS_DEBUG, " done.\n"); |
| 43 | |
| 44 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 45 | /* No reset */ |
| 46 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); |
| 47 | /* halt timer */ |
| 48 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); |
| 49 | /* halt timer */ |
| 50 | outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, |
| 51 | DEFAULT_PMBASE | 0x60 | 0x06); |
| 52 | printk(BIOS_DEBUG, " done.\n"); |
| 53 | |
| 54 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 55 | /* Set up all hardcoded northbridge BARs */ |
| 56 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 57 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, |
| 58 | (0LL + DEFAULT_EPBAR) >> 32); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 59 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 60 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 61 | (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 62 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 63 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 64 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 65 | (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 66 | |
| 67 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 68 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); |
| 69 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33); |
| 70 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33); |
| 71 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33); |
| 72 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33); |
| 73 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); |
| 74 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); |
| 75 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 76 | printk(BIOS_DEBUG, " done.\n"); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static void early_cpu_init (void) |
| 80 | { |
| 81 | msr_t m; |
| 82 | |
| 83 | /* bit 0 = disable multicore, |
| 84 | bit 1 = disable quadcore, |
| 85 | bit 8 = disable hyperthreading. */ |
| 86 | pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80, |
| 87 | (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000); |
| 88 | |
| 89 | u8 reg8; |
| 90 | struct cpuid_result result; |
| 91 | result = cpuid_ext(0x6, 0x8b); |
| 92 | if (!(result.eax & 0x2)) { |
| 93 | m = rdmsr(MSR_FSB_CLOCK_VCC); |
| 94 | reg8 = ((m.lo & 0xff00) >> 8) + 1; |
Elyes HAOUAS | 4fe0cba | 2018-10-17 20:20:39 +0200 | [diff] [blame] | 95 | m = rdmsr(IA32_PERF_CTL); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 96 | m.lo = (m.lo & ~0xff) | reg8; |
| 97 | wrmsr(IA32_PERF_CTL, m); |
| 98 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 99 | m = rdmsr(IA32_MISC_ENABLE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 100 | m.hi &= ~0x00000040; |
| 101 | m.lo |= 0x10000; |
| 102 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 103 | wrmsr(IA32_MISC_ENABLE, m); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | m = rdmsr(MSR_FSB_CLOCK_VCC); |
| 107 | reg8 = ((m.lo & 0xff00) >> 8) + 1; |
| 108 | |
Elyes HAOUAS | 4fe0cba | 2018-10-17 20:20:39 +0200 | [diff] [blame] | 109 | m = rdmsr(IA32_PERF_CTL); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 110 | m.lo = (m.lo & ~0xff) | reg8; |
| 111 | wrmsr(IA32_PERF_CTL, m); |
| 112 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 113 | m = rdmsr(IA32_MISC_ENABLE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 114 | m.lo |= 0x10000; |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 115 | wrmsr(IA32_MISC_ENABLE, m); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | void nehalem_early_initialization(int chipset_type) |
| 119 | { |
| 120 | u32 capid0_a; |
| 121 | u8 reg8; |
Kyösti Mälkki | 2cce24d | 2019-09-11 10:47:39 +0300 | [diff] [blame] | 122 | int s3_resume; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 123 | |
| 124 | /* Device ID Override Enable should be done very early */ |
| 125 | capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); |
| 126 | if (capid0_a & (1 << 10)) { |
| 127 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); |
| 128 | reg8 &= ~7; /* Clear 2:0 */ |
| 129 | |
| 130 | if (chipset_type == NEHALEM_MOBILE) |
| 131 | reg8 |= 1; /* Set bit 0 */ |
| 132 | |
| 133 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); |
| 134 | } |
| 135 | |
| 136 | /* Setup all BARs required for early PCIe and raminit */ |
| 137 | nehalem_setup_bars(); |
| 138 | |
Kyösti Mälkki | 2cce24d | 2019-09-11 10:47:39 +0300 | [diff] [blame] | 139 | s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 140 | (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); |
| 141 | |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame^] | 142 | elog_boot_notify(s3_resume); |
Kyösti Mälkki | 2cce24d | 2019-09-11 10:47:39 +0300 | [diff] [blame] | 143 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 144 | /* Device Enable */ |
Patrick Rudolph | 847f12b | 2018-06-14 16:00:19 +0200 | [diff] [blame] | 145 | pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, |
| 146 | DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 147 | |
| 148 | early_cpu_init(); |
| 149 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 150 | pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 151 | pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, |
| 152 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Vladimir Serbinenko | bca9855 | 2014-01-09 11:13:18 +0100 | [diff] [blame] | 153 | |
| 154 | /* Magic for S3 resume. Must be done early. */ |
Kyösti Mälkki | 2cce24d | 2019-09-11 10:47:39 +0300 | [diff] [blame] | 155 | if (s3_resume) { |
Vladimir Serbinenko | bca9855 | 2014-01-09 11:13:18 +0100 | [diff] [blame] | 156 | MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; |
| 157 | MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; |
| 158 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 159 | } |