commit 4fe0cbac97de9519be543ce8956cc7becce62830
author Elyes HAOUAS <ehaouas@noos.fr> Wed Oct 17 20:20:39 2018 +0200
committer Patrick Georgi <pgeorgi@google.com> Fri Oct 19 09:20:34 2018 +0000
tree 2770739472df8d1e4020454a66aa0539ef34e7c4
parent d50cf23e43bb2e54210b2e719bbf53002814926b

nb/intel/nehalem: Remove unneeded whitespace

Change-Id: I942a054144e05a3722c3743e445a879e86021dd4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/northbridge/intel/nehalem/early_init.c

diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 1ebb2a5..59c7741 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -106,7 +106,7 @@
 	if (!(result.eax & 0x2)) {
 		m = rdmsr(MSR_FSB_CLOCK_VCC);
 		reg8 = ((m.lo & 0xff00) >> 8) + 1;
-		m = rdmsr (IA32_PERF_CTL);
+		m = rdmsr(IA32_PERF_CTL);
 		m.lo = (m.lo & ~0xff) | reg8;
 		wrmsr(IA32_PERF_CTL, m);
 
@@ -120,7 +120,7 @@
 	m = rdmsr(MSR_FSB_CLOCK_VCC);
 	reg8 = ((m.lo & 0xff00) >> 8) + 1;
 
-	m = rdmsr (IA32_PERF_CTL);
+	m = rdmsr(IA32_PERF_CTL);
 	m.lo = (m.lo & ~0xff) | reg8;
 	wrmsr(IA32_PERF_CTL, m);