Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame^] | 2 | * This file is part of the coreboot project. |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 21 | /* TODO: Check if this really works for all of the southbridges. */ |
| 22 | |
| 23 | #include <stdint.h> |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 24 | #include <console/console.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include "i82371eb.h" |
| 29 | |
| 30 | /** |
| 31 | * Initialize the IDE controller. |
| 32 | * |
| 33 | * Depending on the configuration variables 'ide0_enable' and 'ide1_enable' |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 34 | * enable or disable the primary and secondary IDE interface, respectively. |
| 35 | * |
| 36 | * Depending on the configuration variable 'ide_legacy_enable' enable or |
| 37 | * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O |
| 38 | * registers (this is required for e.g. FILO). |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 39 | * |
| 40 | * @param dev The device to use. |
| 41 | */ |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 42 | static void ide_init_enable(struct device *dev) |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 43 | { |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 44 | u16 reg16; |
Uwe Hermann | 56a9125 | 2007-06-03 16:57:27 +0000 | [diff] [blame] | 45 | struct southbridge_intel_i82371eb_config *conf = dev->chip_info; |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 46 | |
| 47 | /* Enable/disable the primary IDE interface. */ |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 48 | reg16 = pci_read_config16(dev, IDETIM_PRI); |
| 49 | reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE); |
| 50 | pci_write_config16(dev, IDETIM_PRI, reg16); |
| 51 | printk_debug("IDE: %s: %s\n", "Primary IDE interface", |
| 52 | conf->ide0_enable ? "on" : "off"); |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 53 | |
| 54 | /* Enable/disable the secondary IDE interface. */ |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 55 | reg16 = pci_read_config16(dev, IDETIM_SEC); |
| 56 | reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE); |
| 57 | pci_write_config16(dev, IDETIM_SEC, reg16); |
| 58 | printk_debug("IDE: %s: %s\n", "Secondary IDE interface", |
| 59 | conf->ide1_enable ? "on" : "off"); |
| 60 | |
| 61 | /* Enable access to the legacy IDE ports (both primary and secondary), |
| 62 | * and the PCI Bus Master IDE I/O registers. |
| 63 | * Only do this if at least one IDE interface is enabled. |
| 64 | */ |
| 65 | if (conf->ide0_enable || conf->ide1_enable) { |
| 66 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 67 | reg16 = ONOFF(conf->ide_legacy_enable, reg16, |
| 68 | (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); |
| 69 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 70 | printk_debug("IDE: Access to legacy IDE ports: %s\n", |
| 71 | conf->ide_legacy_enable ? "on" : "off"); |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 72 | } |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 73 | } |
| 74 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 75 | /** |
| 76 | * Initialize the Ultra DMA/33 support of the IDE controller. |
| 77 | * |
| 78 | * Depending on the configuration variables 'ide0_drive0_udma33_enable', |
| 79 | * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and |
| 80 | * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for |
| 81 | * the respective IDE controller and drive. |
| 82 | * |
| 83 | * Only do that if the respective controller is actually enabled, of course. |
| 84 | * |
| 85 | * @param dev The device to use. |
| 86 | */ |
| 87 | static void ide_init_udma33(struct device *dev) |
| 88 | { |
| 89 | u8 reg8; |
| 90 | struct southbridge_intel_i82371eb_config *conf = dev->chip_info; |
| 91 | |
| 92 | /* Enable/disable UDMA/33 operation (primary IDE interface). */ |
| 93 | if (conf->ide0_enable) { |
| 94 | reg8 = pci_read_config8(dev, UDMACTL); |
| 95 | reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0); |
| 96 | reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1); |
| 97 | pci_write_config8(dev, UDMACTL, reg8); |
| 98 | |
| 99 | printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", |
| 100 | "Primary IDE interface", 0, |
| 101 | conf->ide0_drive0_udma33_enable ? "on" : "off"); |
| 102 | printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", |
| 103 | "Primary IDE interface", 1, |
| 104 | conf->ide0_drive1_udma33_enable ? "on" : "off"); |
| 105 | } |
| 106 | |
| 107 | /* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */ |
| 108 | if (conf->ide1_enable) { |
| 109 | reg8 = pci_read_config8(dev, UDMACTL); |
| 110 | reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0); |
| 111 | reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1); |
| 112 | pci_write_config8(dev, UDMACTL, reg8); |
| 113 | |
| 114 | printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", |
| 115 | "Secondary IDE interface", 0, |
| 116 | conf->ide1_drive0_udma33_enable ? "on" : "off"); |
| 117 | printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", |
| 118 | "Secondary IDE interface", 1, |
| 119 | conf->ide1_drive1_udma33_enable ? "on" : "off"); |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | /** |
| 124 | * IDE init for the Intel 82371FB/SB IDE controller. |
| 125 | * |
| 126 | * These devices do not support UDMA/33, so don't attempt to enable it. |
| 127 | * |
| 128 | * @param dev The device to use. |
| 129 | */ |
| 130 | static void ide_init_i82371fb_sb(struct device *dev) |
| 131 | { |
| 132 | ide_init_enable(dev); |
| 133 | } |
| 134 | |
| 135 | /** |
| 136 | * IDE init for the Intel 82371AB/EB/MB IDE controller. |
| 137 | * |
| 138 | * @param dev The device to use. |
| 139 | */ |
| 140 | static void ide_init_i82371ab_eb_mb(struct device *dev) |
| 141 | { |
| 142 | ide_init_enable(dev); |
| 143 | ide_init_udma33(dev); |
| 144 | } |
| 145 | |
| 146 | /* Intel 82371FB/SB */ |
| 147 | static const struct device_operations ide_ops_fb_sb = { |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 148 | .read_resources = pci_dev_read_resources, |
| 149 | .set_resources = pci_dev_set_resources, |
| 150 | .enable_resources = pci_dev_enable_resources, |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 151 | .init = ide_init_i82371fb_sb, |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 152 | .scan_bus = 0, |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 153 | .enable = 0, |
| 154 | .ops_pci = 0, /* No subsystem IDs on 82371XX! */ |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 155 | }; |
| 156 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 157 | /* Intel 82371AB/EB/MB */ |
| 158 | static const struct device_operations ide_ops_ab_eb_mb = { |
| 159 | .read_resources = pci_dev_read_resources, |
| 160 | .set_resources = pci_dev_set_resources, |
| 161 | .enable_resources = pci_dev_enable_resources, |
| 162 | .init = ide_init_i82371ab_eb_mb, |
| 163 | .scan_bus = 0, |
| 164 | .enable = 0, |
| 165 | .ops_pci = 0, /* No subsystem IDs on 82371XX! */ |
| 166 | }; |
| 167 | |
| 168 | /* Intel 82371FB (PIIX) */ |
| 169 | static const struct pci_driver ide_driver_fb __pci_driver = { |
| 170 | .ops = &ide_ops_fb_sb, |
| 171 | .vendor = PCI_VENDOR_ID_INTEL, |
| 172 | .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, |
| 173 | }; |
| 174 | |
| 175 | /* Intel 82371SB (PIIX3) */ |
| 176 | static const struct pci_driver ide_driver_sb __pci_driver = { |
| 177 | .ops = &ide_ops_fb_sb, |
| 178 | .vendor = PCI_VENDOR_ID_INTEL, |
| 179 | .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, |
| 180 | }; |
| 181 | |
| 182 | /* Intel 82371MX (MPIIX) */ |
| 183 | static const struct pci_driver ide_driver_mx __pci_driver = { |
| 184 | .ops = &ide_ops_fb_sb, |
| 185 | .vendor = PCI_VENDOR_ID_INTEL, |
| 186 | .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, |
| 187 | }; |
| 188 | |
| 189 | /* Intel 82437MX (part of the 430MX chipset) */ |
| 190 | static const struct pci_driver ide_driver_82437mx __pci_driver = { |
| 191 | .ops = &ide_ops_fb_sb, |
| 192 | .vendor = PCI_VENDOR_ID_INTEL, |
| 193 | .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, |
| 194 | }; |
| 195 | |
| 196 | /* Intel 82371AB/EB/MB */ |
| 197 | static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { |
| 198 | .ops = &ide_ops_ab_eb_mb, |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 199 | .vendor = PCI_VENDOR_ID_INTEL, |
| 200 | .device = PCI_DEVICE_ID_INTEL_82371AB_IDE, |
| 201 | }; |