Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Karthikeyan Ramasubramanian | f8b237b | 2021-06-16 17:37:38 -0600 | [diff] [blame] | 3 | #include <baseboard/variants.h> |
Karthikeyan Ramasubramanian | 0bf9afe | 2021-10-15 16:36:07 -0600 | [diff] [blame] | 4 | #include <device/device.h> |
Karthikeyan Ramasubramanian | f8b237b | 2021-06-16 17:37:38 -0600 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 6 | #include <soc/platform_descriptors.h> |
Martin Roth | d76b4f6 | 2021-04-05 17:24:51 -0600 | [diff] [blame] | 7 | #include <soc/gpio.h> |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 8 | #include <types.h> |
| 9 | |
Martin Roth | 76643f0 | 2021-08-31 17:46:27 -0600 | [diff] [blame] | 10 | /* All PCIe Resets are handled in coreboot */ |
Karthikeyan Ramasubramanian | 0bf9afe | 2021-10-15 16:36:07 -0600 | [diff] [blame] | 11 | static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { |
Martin Roth | 76643f0 | 2021-08-31 17:46:27 -0600 | [diff] [blame] | 12 | { /* WLAN */ |
| 13 | .engine_type = PCIE_ENGINE, |
| 14 | .port_present = true, |
| 15 | .start_logical_lane = 0, |
| 16 | .end_logical_lane = 0, |
Matt Papageorge | 7d6b4e3 | 2021-11-01 16:39:47 -0500 | [diff] [blame^] | 17 | .link_speed_capability = 3, |
Martin Roth | 76643f0 | 2021-08-31 17:46:27 -0600 | [diff] [blame] | 18 | .device_number = PCI_SLOT(WLAN_DEVFN), |
| 19 | .function_number = PCI_FUNC(WLAN_DEVFN), |
| 20 | .link_aspm = ASPM_L1, |
| 21 | .link_aspm_L1_1 = true, |
| 22 | .link_aspm_L1_2 = true, |
| 23 | .turn_off_unused_lanes = true, |
| 24 | .clk_req = CLK_REQ0, |
| 25 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 26 | }, |
| 27 | { /* SD */ |
| 28 | .engine_type = PCIE_ENGINE, |
| 29 | .port_present = true, |
| 30 | .start_logical_lane = 1, |
| 31 | .end_logical_lane = 1, |
Matt Papageorge | 7d6b4e3 | 2021-11-01 16:39:47 -0500 | [diff] [blame^] | 32 | .link_speed_capability = 3, |
Martin Roth | 76643f0 | 2021-08-31 17:46:27 -0600 | [diff] [blame] | 33 | .device_number = PCI_SLOT(SD_DEVFN), |
| 34 | .function_number = PCI_FUNC(SD_DEVFN), |
| 35 | .link_aspm = ASPM_L1, |
| 36 | .link_aspm_L1_1 = true, |
| 37 | .link_aspm_L1_2 = true, |
| 38 | .turn_off_unused_lanes = true, |
| 39 | .clk_req = CLK_REQ1, |
Matt Papageorge | cc2fa98 | 2021-10-08 13:30:23 -0500 | [diff] [blame] | 40 | .gpio_group_id = GPIO_69, |
Martin Roth | 76643f0 | 2021-08-31 17:46:27 -0600 | [diff] [blame] | 41 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 42 | }, |
| 43 | { /* WWAN */ |
| 44 | .engine_type = UNUSED_ENGINE, |
| 45 | .port_present = true, |
| 46 | .start_logical_lane = 2, |
| 47 | .end_logical_lane = 2, |
Matt Papageorge | 7d6b4e3 | 2021-11-01 16:39:47 -0500 | [diff] [blame^] | 48 | .link_speed_capability = 3, |
Martin Roth | 76643f0 | 2021-08-31 17:46:27 -0600 | [diff] [blame] | 49 | .device_number = PCI_SLOT(WWAN_DEVFN), |
| 50 | .function_number = PCI_FUNC(WWAN_DEVFN), |
| 51 | .link_aspm = ASPM_L1, |
| 52 | .link_aspm_L1_1 = true, |
| 53 | .link_aspm_L1_2 = true, |
| 54 | .turn_off_unused_lanes = true, |
| 55 | .clk_req = CLK_REQ2, |
| 56 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 57 | }, |
| 58 | { /* NVME */ |
| 59 | .engine_type = PCIE_ENGINE, |
| 60 | .port_present = true, |
| 61 | .start_logical_lane = 4, |
| 62 | .end_logical_lane = 7, |
Matt Papageorge | 7d6b4e3 | 2021-11-01 16:39:47 -0500 | [diff] [blame^] | 63 | .link_speed_capability = 3, |
Martin Roth | 76643f0 | 2021-08-31 17:46:27 -0600 | [diff] [blame] | 64 | .device_number = PCI_SLOT(NVME_DEVFN), |
| 65 | .function_number = PCI_FUNC(NVME_DEVFN), |
| 66 | .link_aspm = ASPM_L1, |
| 67 | .link_aspm_L1_1 = true, |
| 68 | .link_aspm_L1_2 = true, |
| 69 | .turn_off_unused_lanes = true, |
| 70 | .clk_req = CLK_REQ3, |
| 71 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 72 | }, |
| 73 | { /* TODO: remove this temporary workaround */ |
| 74 | .engine_type = PCIE_ENGINE, |
| 75 | .port_present = true, |
| 76 | .start_logical_lane = 8, |
| 77 | .end_logical_lane = 11, |
| 78 | .device_number = PCIE_GPP_BRIDGE_2_DEV, |
| 79 | .function_number = PCIE_GPP_2_4_FUNC, |
| 80 | .turn_off_unused_lanes = true, |
| 81 | .clk_req = CLK_REQ5, |
| 82 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 83 | }, |
| 84 | { /* TODO: remove this temporary workaround */ |
Felix Held | c81fb7c | 2021-04-06 22:17:12 +0200 | [diff] [blame] | 85 | .engine_type = PCIE_ENGINE, |
| 86 | .port_present = true, |
| 87 | .start_logical_lane = 16, |
| 88 | .end_logical_lane = 23, |
Karthikeyan Ramasubramanian | f8b237b | 2021-06-16 17:37:38 -0600 | [diff] [blame] | 89 | .device_number = PCIE_GPP_BRIDGE_1_DEV, |
| 90 | .function_number = PCIE_GPP_1_0_FUNC, |
Felix Held | c81fb7c | 2021-04-06 22:17:12 +0200 | [diff] [blame] | 91 | .turn_off_unused_lanes = true, |
| 92 | .clk_req = CLK_REQ6, |
| 93 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
Felix Held | 6478cf9 | 2021-03-30 23:20:08 +0200 | [diff] [blame] | 94 | } |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 95 | }; |
| 96 | |
Felix Held | 6478cf9 | 2021-03-30 23:20:08 +0200 | [diff] [blame] | 97 | /* TODO: verify the DDI table, since this is mostly an educated guess right now */ |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 98 | static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { |
Felix Held | 6478cf9 | 2021-03-30 23:20:08 +0200 | [diff] [blame] | 99 | { /* DDI0 - eDP */ |
| 100 | .connector_type = DDI_EDP, |
| 101 | .aux_index = DDI_AUX1, |
| 102 | .hdp_index = DDI_HDP1 |
| 103 | }, |
| 104 | { /* DDI1 - HDMI */ |
| 105 | .connector_type = DDI_HDMI, |
| 106 | .aux_index = DDI_AUX2, |
| 107 | .hdp_index = DDI_HDP2 |
| 108 | }, |
| 109 | { /* DDI2 */ |
| 110 | .connector_type = DDI_UNUSED_TYPE, |
| 111 | .aux_index = DDI_AUX3, |
| 112 | .hdp_index = DDI_HDP3, |
| 113 | }, |
| 114 | { /* DDI3 - DP (type C) */ |
| 115 | .connector_type = DDI_DP, |
| 116 | .aux_index = DDI_AUX3, |
| 117 | .hdp_index = DDI_HDP3, |
| 118 | }, |
| 119 | { /* DDI4 - DP (type C) */ |
| 120 | .connector_type = DDI_DP, |
| 121 | .aux_index = DDI_AUX4, |
| 122 | .hdp_index = DDI_HDP4, |
| 123 | } |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 124 | }; |
| 125 | |
Kevin Chiu | 1a950d6 | 2021-10-18 19:45:37 +0800 | [diff] [blame] | 126 | void __weak variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) |
| 127 | { |
| 128 | } |
| 129 | |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 130 | void mainboard_get_dxio_ddi_descriptors( |
| 131 | const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, |
| 132 | const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) |
| 133 | { |
Karthikeyan Ramasubramanian | 750abb1 | 2021-10-25 22:50:33 -0600 | [diff] [blame] | 134 | /* Get Variant specific SD AUX Reset GPIO */ |
| 135 | guybrush_czn_dxio_descriptors[SD].gpio_group_id = variant_sd_aux_reset_gpio(); |
| 136 | |
Karthikeyan Ramasubramanian | 0bf9afe | 2021-10-15 16:36:07 -0600 | [diff] [blame] | 137 | /* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it |
| 138 | is enabled. */ |
| 139 | if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) |
| 140 | guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE; |
| 141 | |
Karthikeyan Ramasubramanian | 72cc046 | 2021-10-19 15:38:36 -0600 | [diff] [blame] | 142 | if (variant_has_pcie_wwan()) |
| 143 | guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18; |
| 144 | |
Kevin Chiu | 1a950d6 | 2021-10-18 19:45:37 +0800 | [diff] [blame] | 145 | variant_update_dxio_descriptors(guybrush_czn_dxio_descriptors); |
| 146 | |
Karthikeyan Ramasubramanian | 0bf9afe | 2021-10-15 16:36:07 -0600 | [diff] [blame] | 147 | *dxio_descs = guybrush_czn_dxio_descriptors; |
| 148 | *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); |
Martin Roth | 76643f0 | 2021-08-31 17:46:27 -0600 | [diff] [blame] | 149 | |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 150 | *ddi_descs = guybrush_czn_ddi_descriptors; |
| 151 | *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); |
| 152 | } |