Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <soc/platform_descriptors.h> |
| 4 | #include <types.h> |
| 5 | |
Felix Held | 6478cf9 | 2021-03-30 23:20:08 +0200 | [diff] [blame^] | 6 | /* TODO: test if this really works */ |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 7 | static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { |
Felix Held | 6478cf9 | 2021-03-30 23:20:08 +0200 | [diff] [blame^] | 8 | { /* WLAN */ |
| 9 | .engine_type = PCIE_ENGINE, |
| 10 | .port_present = true, |
| 11 | .start_logical_lane = 0, |
| 12 | .end_logical_lane = 0, |
| 13 | .device_number = 2, |
| 14 | .function_number = 1, |
| 15 | .turn_off_unused_lanes = true, |
| 16 | .clk_req = CLK_REQ0, |
| 17 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 18 | }, |
| 19 | { /* SD */ |
| 20 | .engine_type = PCIE_ENGINE, |
| 21 | .port_present = true, |
| 22 | .start_logical_lane = 1, |
| 23 | .end_logical_lane = 1, |
| 24 | .device_number = 2, |
| 25 | .function_number = 2, |
| 26 | .turn_off_unused_lanes = true, |
| 27 | .clk_req = CLK_REQ1, |
| 28 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 29 | }, |
| 30 | { /* WWAN */ |
| 31 | .engine_type = PCIE_ENGINE, |
| 32 | .port_present = true, |
| 33 | .start_logical_lane = 2, |
| 34 | .end_logical_lane = 2, |
| 35 | .device_number = 2, |
| 36 | .function_number = 3, |
| 37 | .turn_off_unused_lanes = true, |
| 38 | .clk_req = CLK_REQ2, |
| 39 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 40 | }, |
| 41 | { /* NVME */ |
| 42 | .engine_type = PCIE_ENGINE, |
| 43 | .port_present = true, |
| 44 | .start_logical_lane = 4, |
| 45 | .end_logical_lane = 7, |
| 46 | .device_number = 2, |
| 47 | .function_number = 4, |
| 48 | .turn_off_unused_lanes = true, |
| 49 | .clk_req = CLK_REQ3, |
| 50 | .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |
| 51 | } |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 52 | }; |
| 53 | |
Felix Held | 6478cf9 | 2021-03-30 23:20:08 +0200 | [diff] [blame^] | 54 | /* TODO: verify the DDI table, since this is mostly an educated guess right now */ |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 55 | static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { |
Felix Held | 6478cf9 | 2021-03-30 23:20:08 +0200 | [diff] [blame^] | 56 | { /* DDI0 - eDP */ |
| 57 | .connector_type = DDI_EDP, |
| 58 | .aux_index = DDI_AUX1, |
| 59 | .hdp_index = DDI_HDP1 |
| 60 | }, |
| 61 | { /* DDI1 - HDMI */ |
| 62 | .connector_type = DDI_HDMI, |
| 63 | .aux_index = DDI_AUX2, |
| 64 | .hdp_index = DDI_HDP2 |
| 65 | }, |
| 66 | { /* DDI2 */ |
| 67 | .connector_type = DDI_UNUSED_TYPE, |
| 68 | .aux_index = DDI_AUX3, |
| 69 | .hdp_index = DDI_HDP3, |
| 70 | }, |
| 71 | { /* DDI3 - DP (type C) */ |
| 72 | .connector_type = DDI_DP, |
| 73 | .aux_index = DDI_AUX3, |
| 74 | .hdp_index = DDI_HDP3, |
| 75 | }, |
| 76 | { /* DDI4 - DP (type C) */ |
| 77 | .connector_type = DDI_DP, |
| 78 | .aux_index = DDI_AUX4, |
| 79 | .hdp_index = DDI_HDP4, |
| 80 | } |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 81 | }; |
| 82 | |
| 83 | void mainboard_get_dxio_ddi_descriptors( |
| 84 | const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, |
| 85 | const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) |
| 86 | { |
| 87 | *dxio_descs = guybrush_czn_dxio_descriptors; |
| 88 | *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); |
| 89 | *ddi_descs = guybrush_czn_ddi_descriptors; |
| 90 | *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); |
| 91 | } |