Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <cbfs.h> |
| 5 | #include <console/console.h> |
| 6 | #include <cpu/intel/cpu_ids.h> |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 7 | #include <cpu/intel/microcode.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <fsp/api.h> |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 11 | #include <fsp/fsp_debug_event.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 12 | #include <fsp/ppi/mp_service_ppi.h> |
| 13 | #include <fsp/util.h> |
Dinesh Gehlot | e7c1f7d | 2022-12-06 10:58:48 +0000 | [diff] [blame] | 14 | #include <option.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 15 | #include <intelblocks/cse.h> |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 16 | #include <intelblocks/irq.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 17 | #include <intelblocks/lpss.h> |
Subrata Banik | f251a6a | 2022-12-11 16:39:05 +0530 | [diff] [blame] | 18 | #include <intelblocks/mp_init.h> |
| 19 | #include <intelblocks/systemagent.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 20 | #include <intelblocks/xdci.h> |
| 21 | #include <intelpch/lockdown.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 22 | #include <security/vboot/vboot_common.h> |
John Zhao | 54a03e4 | 2022-08-03 20:07:03 -0700 | [diff] [blame] | 23 | #include <soc/cpu.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 24 | #include <soc/gpio_soc_defs.h> |
| 25 | #include <soc/intel/common/vbt.h> |
| 26 | #include <soc/pci_devs.h> |
| 27 | #include <soc/pcie.h> |
| 28 | #include <soc/ramstage.h> |
| 29 | #include <soc/soc_chip.h> |
| 30 | #include <soc/soc_info.h> |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 31 | #include <stdlib.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 32 | #include <string.h> |
Dinesh Gehlot | e7c1f7d | 2022-12-06 10:58:48 +0000 | [diff] [blame] | 33 | #include <types.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 34 | |
| 35 | /* THC assignment definition */ |
| 36 | #define THC_NONE 0 |
| 37 | #define THC_0 1 |
| 38 | #define THC_1 2 |
| 39 | |
| 40 | /* SATA DEVSLP idle timeout default values */ |
| 41 | #define DEF_DMVAL 15 |
| 42 | #define DEF_DITOVAL 625 |
| 43 | |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 44 | static const struct slot_irq_constraints irq_constraints[] = { |
| 45 | { |
| 46 | .slot = PCI_DEV_SLOT_PCIE_3, |
| 47 | .fns = { |
| 48 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_A, PIRQ_A), |
| 49 | }, |
| 50 | }, |
| 51 | { |
| 52 | .slot = PCI_DEV_SLOT_IGD, |
| 53 | .fns = { |
| 54 | /* INTERRUPT_PIN is RO/0x01 */ |
| 55 | FIXED_INT_ANY_PIRQ(PCI_DEV_SLOT_IGD, PCI_INT_A), |
| 56 | }, |
| 57 | }, |
| 58 | { |
| 59 | .slot = PCI_DEV_SLOT_DPTF, |
| 60 | .fns = { |
| 61 | ANY_PIRQ(PCI_DEVFN_DPTF), |
| 62 | }, |
| 63 | }, |
| 64 | { |
| 65 | .slot = PCI_DEV_SLOT_IPU, |
| 66 | .fns = { |
| 67 | /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, |
| 68 | but S0ix fails when not set to 16 (b/193434192) */ |
| 69 | FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A), |
| 70 | }, |
| 71 | }, |
| 72 | { |
| 73 | .slot = PCI_DEV_SLOT_PCIE_2, |
| 74 | .fns = { |
| 75 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 76 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 77 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 78 | }, |
| 79 | }, |
| 80 | { |
| 81 | .slot = PCI_DEV_SLOT_TBT, |
| 82 | .fns = { |
| 83 | ANY_PIRQ(PCI_DEVFN_TBT0), |
| 84 | ANY_PIRQ(PCI_DEVFN_TBT1), |
| 85 | ANY_PIRQ(PCI_DEVFN_TBT2), |
| 86 | ANY_PIRQ(PCI_DEVFN_TBT3), |
| 87 | }, |
| 88 | }, |
| 89 | { |
| 90 | .slot = PCI_DEV_SLOT_GNA, |
| 91 | .fns = { |
| 92 | /* INTERRUPT_PIN is RO/0x01 */ |
| 93 | FIXED_INT_ANY_PIRQ(PCI_DEVFN_GNA, PCI_INT_A), |
| 94 | }, |
| 95 | }, |
| 96 | { |
| 97 | .slot = PCI_DEV_SLOT_VPU, |
| 98 | .fns = { |
| 99 | /* INTERRUPT_PIN is RO/0x01 */ |
| 100 | FIXED_INT_ANY_PIRQ(PCI_DEVFN_VPU, PCI_INT_A), |
| 101 | }, |
| 102 | }, |
| 103 | { |
| 104 | .slot = PCI_DEV_SLOT_TCSS, |
| 105 | .fns = { |
| 106 | ANY_PIRQ(PCI_DEVFN_TCSS_XHCI), |
| 107 | ANY_PIRQ(PCI_DEVFN_TCSS_XDCI), |
| 108 | }, |
| 109 | }, |
| 110 | { |
| 111 | .slot = PCI_DEV_SLOT_THC, |
| 112 | .fns = { |
| 113 | ANY_PIRQ(PCI_DEVFN_THC0), |
| 114 | ANY_PIRQ(PCI_DEVFN_THC1), |
| 115 | }, |
| 116 | }, |
| 117 | { |
| 118 | .slot = PCI_DEV_SLOT_ISH, |
| 119 | .fns = { |
| 120 | DIRECT_IRQ(PCI_DEVFN_ISH), |
| 121 | DIRECT_IRQ(PCI_DEVFN_GSPI2), |
| 122 | ANY_PIRQ(PCI_DEVFN_UFS), |
| 123 | }, |
| 124 | }, |
| 125 | { |
| 126 | .slot = PCI_DEV_SLOT_XHCI, |
| 127 | .fns = { |
| 128 | ANY_PIRQ(PCI_DEVFN_XHCI), |
| 129 | DIRECT_IRQ(PCI_DEVFN_USBOTG), |
| 130 | ANY_PIRQ(PCI_DEVFN_CNVI_WIFI), |
| 131 | }, |
| 132 | }, |
| 133 | { |
| 134 | .slot = PCI_DEV_SLOT_SIO0, |
| 135 | .fns = { |
| 136 | DIRECT_IRQ(PCI_DEVFN_I2C0), |
| 137 | DIRECT_IRQ(PCI_DEVFN_I2C1), |
| 138 | DIRECT_IRQ(PCI_DEVFN_I2C2), |
| 139 | DIRECT_IRQ(PCI_DEVFN_I2C3), |
| 140 | }, |
| 141 | }, |
| 142 | { |
| 143 | .slot = PCI_DEV_SLOT_CSE, |
| 144 | .fns = { |
| 145 | ANY_PIRQ(PCI_DEVFN_CSE), |
| 146 | ANY_PIRQ(PCI_DEVFN_CSE_2), |
| 147 | ANY_PIRQ(PCI_DEVFN_CSE_IDER), |
| 148 | ANY_PIRQ(PCI_DEVFN_CSE_KT), |
| 149 | ANY_PIRQ(PCI_DEVFN_CSE_3), |
| 150 | ANY_PIRQ(PCI_DEVFN_CSE_4), |
| 151 | }, |
| 152 | }, |
| 153 | { |
| 154 | .slot = PCI_DEV_SLOT_SATA, |
| 155 | .fns = { |
| 156 | ANY_PIRQ(PCI_DEVFN_SATA), |
| 157 | }, |
| 158 | }, |
| 159 | { |
| 160 | .slot = PCI_DEV_SLOT_SIO1, |
| 161 | .fns = { |
| 162 | DIRECT_IRQ(PCI_DEVFN_I2C4), |
| 163 | DIRECT_IRQ(PCI_DEVFN_I2C5), |
| 164 | DIRECT_IRQ(PCI_DEVFN_UART2), |
| 165 | }, |
| 166 | }, |
| 167 | { |
| 168 | .slot = PCI_DEV_SLOT_PCIE_1, |
| 169 | .fns = { |
| 170 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 171 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 172 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 173 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 174 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 175 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 176 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 177 | FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 178 | }, |
| 179 | }, |
| 180 | { |
| 181 | .slot = PCI_DEV_SLOT_SIO2, |
| 182 | .fns = { |
| 183 | /* UART0 shares an interrupt line with TSN0, so must use |
| 184 | a PIRQ */ |
| 185 | FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART0, PCI_INT_A), |
| 186 | /* UART1 shares an interrupt line with TSN1, so must use |
| 187 | a PIRQ */ |
| 188 | FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART1, PCI_INT_B), |
| 189 | DIRECT_IRQ(PCI_DEVFN_GSPI0), |
| 190 | DIRECT_IRQ(PCI_DEVFN_GSPI1), |
| 191 | }, |
| 192 | }, |
| 193 | { |
| 194 | .slot = PCI_DEV_SLOT_ESPI, |
| 195 | .fns = { |
| 196 | ANY_PIRQ(PCI_DEVFN_HDA), |
| 197 | ANY_PIRQ(PCI_DEVFN_SMBUS), |
| 198 | ANY_PIRQ(PCI_DEVFN_GBE), |
| 199 | /* INTERRUPT_PIN is RO/0x01 */ |
| 200 | FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPK, PCI_INT_A), |
| 201 | }, |
| 202 | }, |
| 203 | }; |
| 204 | |
| 205 | bool is_pch_slot(unsigned int devfn) |
| 206 | { |
| 207 | if (PCI_SLOT(devfn) >= MIN_PCH_SLOT) |
| 208 | return true; |
| 209 | const struct pcie_rp_group *group; |
| 210 | for (group = get_pcie_rp_table(); group->count; ++group) { |
| 211 | if (PCI_SLOT(devfn) == group->slot) |
| 212 | return true; |
| 213 | } |
| 214 | return false; |
| 215 | } |
| 216 | |
| 217 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 218 | { |
| 219 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 220 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 221 | size_t pch_total = 0; |
| 222 | size_t cfg_count = 0; |
| 223 | |
| 224 | if (!entry) |
| 225 | return NULL; |
| 226 | |
| 227 | /* Count PCH devices */ |
| 228 | while (entry) { |
| 229 | if (is_pch_slot(entry->devfn)) |
| 230 | ++pch_total; |
| 231 | entry = entry->next; |
| 232 | } |
| 233 | |
| 234 | /* Convert PCH device entries to FSP format */ |
| 235 | config = calloc(pch_total, sizeof(*config)); |
| 236 | entry = get_cached_pci_irqs(); |
| 237 | while (entry) { |
| 238 | if (!is_pch_slot(entry->devfn)) { |
| 239 | entry = entry->next; |
| 240 | continue; |
| 241 | } |
| 242 | |
| 243 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 244 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 245 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 246 | config[cfg_count].Irq = entry->irq; |
| 247 | ++cfg_count; |
| 248 | |
| 249 | entry = entry->next; |
| 250 | } |
| 251 | |
| 252 | *out_count = cfg_count; |
| 253 | |
| 254 | return config; |
| 255 | } |
| 256 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 257 | /* |
| 258 | * ME End of Post configuration |
| 259 | * 0 - Disable EOP. |
| 260 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 261 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 262 | */ |
| 263 | enum fsp_end_of_post { |
| 264 | EOP_DISABLE = 0, |
| 265 | EOP_PEI = 1, |
| 266 | EOP_DXE = 2, |
| 267 | }; |
| 268 | |
| 269 | static const pci_devfn_t i2c_dev[] = { |
| 270 | PCI_DEVFN_I2C0, |
| 271 | PCI_DEVFN_I2C1, |
| 272 | PCI_DEVFN_I2C2, |
| 273 | PCI_DEVFN_I2C3, |
| 274 | PCI_DEVFN_I2C4, |
| 275 | PCI_DEVFN_I2C5, |
| 276 | }; |
| 277 | |
| 278 | static const pci_devfn_t gspi_dev[] = { |
| 279 | PCI_DEVFN_GSPI0, |
| 280 | PCI_DEVFN_GSPI1, |
Angel Pons | c7c746c | 2022-07-16 12:37:38 +0200 | [diff] [blame] | 281 | PCI_DEVFN_GSPI2, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 282 | }; |
| 283 | |
| 284 | static const pci_devfn_t uart_dev[] = { |
| 285 | PCI_DEVFN_UART0, |
| 286 | PCI_DEVFN_UART1, |
| 287 | PCI_DEVFN_UART2 |
| 288 | }; |
| 289 | |
| 290 | /* |
| 291 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 292 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 293 | * In order to ensure that mainboard setting does not disable L1 substates |
| 294 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 295 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 296 | * value is set in fsp_params. |
| 297 | * 0: Use FSP UPD default |
| 298 | * 1: Disable L1 substates |
| 299 | * 2: Use L1.1 |
| 300 | * 3: Use L1.2 (FSP UPD default) |
| 301 | */ |
| 302 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 303 | { |
Subrata Banik | ad6c407 | 2022-12-21 11:41:33 +0530 | [diff] [blame] | 304 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) |
| 305 | ctl = L1_SS_DISABLED; |
| 306 | else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 307 | ctl = L1_SS_L1_2; |
| 308 | return ctl - 1; |
| 309 | } |
| 310 | |
Dinesh Gehlot | 36b6b05 | 2022-12-12 08:48:14 +0000 | [diff] [blame] | 311 | /* |
| 312 | * get_aspm_control() ensures that the right UPD value is set in fsp_params. |
| 313 | * 0: Disable ASPM |
| 314 | * 1: L0s only |
| 315 | * 2: L1 only |
| 316 | * 3: L0s and L1 |
| 317 | * 4: Auto configuration |
| 318 | */ |
| 319 | static unsigned int get_aspm_control(enum ASPM_control ctl) |
| 320 | { |
| 321 | if (ctl > ASPM_AUTO) |
| 322 | ctl = ASPM_AUTO; |
| 323 | return ctl; |
| 324 | } |
| 325 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 326 | __weak void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) |
| 327 | { |
| 328 | /* Override settings per board. */ |
| 329 | } |
| 330 | |
| 331 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 332 | const struct soc_intel_meteorlake_config *config) |
| 333 | { |
| 334 | int max_port, i; |
| 335 | |
| 336 | max_port = get_max_i2c_port(); |
| 337 | for (i = 0; i < max_port; i++) { |
| 338 | s_cfg->SerialIoI2cMode[i] = is_devfn_enabled(i2c_dev[i]) ? |
| 339 | config->serial_io_i2c_mode[i] : 0; |
| 340 | } |
| 341 | |
| 342 | max_port = get_max_gspi_port(); |
| 343 | for (i = 0; i < max_port; i++) { |
| 344 | s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i]; |
| 345 | s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i]; |
| 346 | s_cfg->SerialIoSpiMode[i] = is_devfn_enabled(gspi_dev[i]) ? |
| 347 | config->serial_io_gspi_mode[i] : 0; |
| 348 | } |
| 349 | |
| 350 | max_port = get_max_uart_port(); |
| 351 | for (i = 0; i < max_port; i++) { |
| 352 | s_cfg->SerialIoUartMode[i] = is_devfn_enabled(uart_dev[i]) ? |
| 353 | config->serial_io_uart_mode[i] : 0; |
| 354 | } |
| 355 | } |
| 356 | |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 357 | static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 358 | const struct soc_intel_meteorlake_config *config) |
| 359 | { |
| 360 | const struct microcode *microcode_file; |
| 361 | size_t microcode_len; |
| 362 | |
| 363 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 364 | microcode_file = intel_microcode_find(); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 365 | |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 366 | if (microcode_file != NULL) { |
| 367 | microcode_len = get_microcode_size(microcode_file); |
| 368 | if (microcode_len != 0) { |
| 369 | /* Update CPU Microcode patch base address/size */ |
| 370 | s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; |
| 371 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
| 372 | } |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 373 | } |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 374 | } |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 375 | |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 376 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 377 | const struct soc_intel_meteorlake_config *config) |
| 378 | { |
Subrata Banik | 848c37d | 2022-12-09 13:38:26 +0530 | [diff] [blame] | 379 | /* |
| 380 | * FIXME: FSP assumes ownership of the APs (Application Processors) |
| 381 | * upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. |
| 382 | * Hence, pass a valid pointer to the CpuMpPpi UPD unconditionally. |
| 383 | * This would avoid APs from getting hijacked by FSP while coreboot |
| 384 | * decides to set SkipMpInit UPD. |
| 385 | */ |
| 386 | s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 387 | |
| 388 | /* |
| 389 | * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature |
| 390 | * programming. |
| 391 | */ |
| 392 | if (CONFIG(MTL_USE_FSP_MP_INIT)) |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 393 | fill_fsps_microcode_params(s_cfg, config); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 394 | } |
| 395 | |
| 396 | |
| 397 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 398 | const struct soc_intel_meteorlake_config *config) |
| 399 | { |
| 400 | /* Load VBT before devicetree-specific config. */ |
| 401 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 402 | |
| 403 | /* Check if IGD is present and fill Graphics init param accordingly */ |
| 404 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD); |
| 405 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Subrata Banik | 4cc8a6c | 2022-09-07 09:48:28 -0700 | [diff] [blame] | 406 | s_cfg->PavpEnable = CONFIG(PAVP); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 410 | const struct soc_intel_meteorlake_config *config) |
| 411 | { |
| 412 | const struct device *tcss_port_arr[] = { |
| 413 | DEV_PTR(tcss_usb3_port1), |
| 414 | DEV_PTR(tcss_usb3_port2), |
| 415 | DEV_PTR(tcss_usb3_port3), |
| 416 | DEV_PTR(tcss_usb3_port4), |
| 417 | }; |
| 418 | |
| 419 | s_cfg->TcssAuxOri = config->tcss_aux_ori; |
| 420 | |
| 421 | /* Explicitly clear this field to avoid using defaults */ |
| 422 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
| 423 | |
| 424 | /* D3Hot and D3Cold for TCSS */ |
| 425 | s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; |
| 426 | s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable; |
| 427 | s_cfg->UsbTcPortEn = 0; |
| 428 | |
| 429 | for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |
| 430 | if (is_dev_enabled(tcss_port_arr[i])) |
| 431 | s_cfg->UsbTcPortEn |= BIT(i); |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 436 | const struct soc_intel_meteorlake_config *config) |
| 437 | { |
| 438 | /* Chipset Lockdown */ |
| 439 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 440 | s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; |
| 441 | s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; |
| 442 | s_cfg->PchUnlockGpioPads = !lockdown_by_fsp; |
| 443 | s_cfg->RtcMemoryLock = lockdown_by_fsp; |
| 444 | s_cfg->SkipPamLock = !lockdown_by_fsp; |
| 445 | |
| 446 | /* coreboot will send EOP before loading payload */ |
| 447 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
| 448 | } |
| 449 | |
| 450 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 451 | const struct soc_intel_meteorlake_config *config) |
| 452 | { |
| 453 | int i, max_port; |
| 454 | |
| 455 | max_port = get_max_usb20_port(); |
| 456 | for (i = 0; i < max_port; i++) { |
| 457 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 458 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 459 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 460 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 461 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 462 | |
| 463 | if (config->usb2_ports[i].enable) |
| 464 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 465 | else |
| 466 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
| 467 | } |
| 468 | |
| 469 | max_port = get_max_usb30_port(); |
| 470 | for (i = 0; i < max_port; i++) { |
| 471 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 472 | if (config->usb3_ports[i].enable) |
| 473 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 474 | else |
| 475 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
| 476 | |
| 477 | if (config->usb3_ports[i].tx_de_emp) { |
| 478 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 479 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 480 | } |
| 481 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 482 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 483 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
| 484 | config->usb3_ports[i].tx_downscale_amp; |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | max_port = get_max_tcss_port(); |
| 489 | for (i = 0; i < max_port; i++) { |
| 490 | s_cfg->PortUsb30Enable[i] = config->tcss_ports[i].enable; |
| 491 | if (config->tcss_ports[i].enable) |
| 492 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 497 | const struct soc_intel_meteorlake_config *config) |
| 498 | { |
| 499 | s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG); |
| 500 | } |
| 501 | |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 502 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 503 | const struct soc_intel_meteorlake_config *config) |
| 504 | { |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 505 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 506 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
| 507 | } |
| 508 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 509 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 510 | const struct soc_intel_meteorlake_config *config) |
| 511 | { |
| 512 | /* SATA */ |
| 513 | s_cfg->SataEnable = is_devfn_enabled(PCI_DEVFN_SATA); |
| 514 | if (s_cfg->SataEnable) { |
| 515 | s_cfg->SataMode = config->sata_mode; |
| 516 | s_cfg->SataSalpSupport = config->sata_salp_support; |
| 517 | memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable, |
| 518 | sizeof(s_cfg->SataPortsEnable)); |
| 519 | memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp, |
| 520 | sizeof(s_cfg->SataPortsDevSlp)); |
| 521 | } |
| 522 | |
| 523 | /* |
| 524 | * Power Optimizer for SATA. |
| 525 | * SataPwrOptimizeDisable is default to 0. |
| 526 | * Boards not needing the optimizers explicitly disables them by setting |
| 527 | * these disable variables to 1 in devicetree overrides. |
| 528 | */ |
| 529 | s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable); |
| 530 | /* |
| 531 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 532 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 533 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 534 | * The default values can be changed from devicetree. |
| 535 | */ |
| 536 | for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) { |
| 537 | if (config->sata_ports_enable_dito_config[i]) { |
| 538 | s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i]; |
| 539 | s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i]; |
| 540 | } |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 545 | const struct soc_intel_meteorlake_config *config) |
| 546 | { |
| 547 | /* Enable TCPU for processor thermal control */ |
| 548 | s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF); |
| 549 | |
| 550 | /* Set TccActivationOffset */ |
| 551 | s_cfg->TccActivationOffset = config->tcc_offset; |
| 552 | } |
| 553 | |
| 554 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 555 | const struct soc_intel_meteorlake_config *config) |
| 556 | { |
| 557 | /* LAN */ |
| 558 | s_cfg->PchLanEnable = is_devfn_enabled(PCI_DEVFN_GBE); |
| 559 | } |
| 560 | |
| 561 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 562 | const struct soc_intel_meteorlake_config *config) |
| 563 | { |
| 564 | /* CNVi */ |
| 565 | s_cfg->CnviMode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI); |
| 566 | s_cfg->CnviBtCore = config->cnvi_bt_core; |
| 567 | s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; |
| 568 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
| 569 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
| 570 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
| 571 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
| 572 | } |
| 573 | |
| 574 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 575 | const struct soc_intel_meteorlake_config *config) |
| 576 | { |
| 577 | /* VMD */ |
| 578 | s_cfg->VmdEnable = is_devfn_enabled(PCI_DEVFN_VMD); |
| 579 | } |
| 580 | |
| 581 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 582 | const struct soc_intel_meteorlake_config *config) |
| 583 | { |
Sridhar Siricilla | cb4d464 | 2022-09-26 12:12:20 +0530 | [diff] [blame] | 584 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
| 585 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(PCI_DEVFN_TBT(i)); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 586 | } |
| 587 | |
| 588 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 589 | const struct soc_intel_meteorlake_config *config) |
| 590 | { |
| 591 | /* Legacy 8254 timer support */ |
Dinesh Gehlot | e7c1f7d | 2022-12-06 10:58:48 +0000 | [diff] [blame] | 592 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 593 | s_cfg->Enable8254ClockGating = !use_8254; |
| 594 | s_cfg->Enable8254ClockGatingOnS3 = !use_8254; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 595 | } |
| 596 | |
Kapil Porwal | 89ea312 | 2022-11-15 19:06:49 +0530 | [diff] [blame] | 597 | static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, |
| 598 | const struct soc_intel_meteorlake_config *config) |
| 599 | { |
| 600 | /* |
| 601 | * Legacy PM ACPI Timer (and TCO Timer) |
| 602 | * This *must* be 1 in any case to keep FSP from |
| 603 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 604 | * 2) disabling the PM ACPI Timer. |
| 605 | * We handle both by ourself! |
| 606 | */ |
| 607 | s_cfg->EnableTcoTimer = 1; |
| 608 | } |
| 609 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 610 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 611 | const struct soc_intel_meteorlake_config *config) |
| 612 | { |
| 613 | int max_port = get_max_pcie_port(); |
| 614 | uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table()); |
| 615 | for (int i = 0; i < max_port; i++) { |
| 616 | if (!(enable_mask & BIT(i))) |
| 617 | continue; |
| 618 | const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i]; |
| 619 | s_cfg->PcieRpL1Substates[i] = |
| 620 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
| 621 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 622 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 623 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) |
| 624 | || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 625 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Dinesh Gehlot | 36b6b05 | 2022-12-12 08:48:14 +0000 | [diff] [blame] | 626 | if (rp_cfg->pcie_rp_aspm) |
| 627 | s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 628 | } |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 629 | s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 630 | } |
| 631 | |
| 632 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 633 | const struct soc_intel_meteorlake_config *config) |
| 634 | { |
Kapil Porwal | 66e44e3 | 2022-11-16 10:19:17 +0530 | [diff] [blame] | 635 | /* Skip setting D0I3 bit for all HECI devices */ |
| 636 | s_cfg->DisableD0I3SettingForHeci = 1; |
| 637 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 638 | s_cfg->Hwp = 1; |
| 639 | s_cfg->Cx = 1; |
| 640 | s_cfg->PsOnEnable = 1; |
Kapil Porwal | ae5ba37 | 2023-01-04 21:49:36 +0530 | [diff] [blame] | 641 | s_cfg->PkgCStateLimit = LIMIT_AUTO; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 642 | /* Enable the energy efficient turbo mode */ |
| 643 | s_cfg->EnergyEfficientTurbo = 1; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 644 | s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); |
Kapil Porwal | ae5bc43 | 2023-01-04 22:03:02 +0530 | [diff] [blame] | 645 | s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 646 | } |
| 647 | |
| 648 | |
| 649 | static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg, |
| 650 | const struct soc_intel_meteorlake_config *config) |
| 651 | { |
| 652 | s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS); |
| 653 | } |
| 654 | |
| 655 | static void fill_fsps_ai_params(FSP_S_CONFIG *s_cfg, |
| 656 | const struct soc_intel_meteorlake_config *config) |
| 657 | { |
| 658 | s_cfg->GnaEnable = is_devfn_enabled(PCI_DEVFN_GNA); |
Srinidhi N Kaushik | 9f6e25d | 2022-08-08 20:38:19 -0700 | [diff] [blame] | 659 | s_cfg->VpuEnable = is_devfn_enabled(PCI_DEVFN_VPU); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 660 | } |
| 661 | |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 662 | static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |
| 663 | const struct soc_intel_meteorlake_config *config) |
| 664 | { |
| 665 | if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) |
| 666 | die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); |
| 667 | |
| 668 | size_t pch_count = 0; |
| 669 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 670 | |
| 671 | s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 672 | s_cfg->NumOfDevIntConfig = pch_count; |
| 673 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 674 | } |
| 675 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 676 | static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) |
| 677 | { |
zhaojohn | 9f5fea9 | 2022-09-20 08:12:47 -0700 | [diff] [blame] | 678 | /* |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 679 | * EnableMultiPhaseSiliconInit for running MultiPhaseSiInit |
| 680 | */ |
zhaojohn | 9f5fea9 | 2022-09-20 08:12:47 -0700 | [diff] [blame] | 681 | s_arch_cfg->EnableMultiPhaseSiliconInit = 1; |
Srinidhi N Kaushik | 9a69002 | 2022-07-25 22:12:34 -0700 | [diff] [blame] | 682 | |
| 683 | /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ |
| 684 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && |
| 685 | CONFIG(FSP_ENABLE_SERIAL_DEBUG)) |
| 686 | s_arch_cfg->FspEventHandler = (FSP_EVENT_HANDLER) |
| 687 | fsp_debug_event_handler; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 688 | } |
| 689 | |
| 690 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 691 | struct soc_intel_meteorlake_config *config) |
| 692 | { |
| 693 | /* Override settings per board if required. */ |
| 694 | mainboard_update_soc_chip_config(config); |
| 695 | |
Arthur Heymans | 4081d6c | 2022-07-29 10:45:52 +0200 | [diff] [blame] | 696 | void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 697 | const struct soc_intel_meteorlake_config *config) = { |
| 698 | fill_fsps_lpss_params, |
| 699 | fill_fsps_cpu_params, |
| 700 | fill_fsps_igd_params, |
| 701 | fill_fsps_tcss_params, |
| 702 | fill_fsps_chipset_lockdown_params, |
| 703 | fill_fsps_xhci_params, |
| 704 | fill_fsps_xdci_params, |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 705 | fill_fsps_uart_params, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 706 | fill_fsps_sata_params, |
| 707 | fill_fsps_thermal_params, |
| 708 | fill_fsps_lan_params, |
| 709 | fill_fsps_cnvi_params, |
| 710 | fill_fsps_vmd_params, |
| 711 | fill_fsps_tbt_params, |
| 712 | fill_fsps_8254_params, |
Kapil Porwal | 89ea312 | 2022-11-15 19:06:49 +0530 | [diff] [blame] | 713 | fill_fsps_pm_timer_params, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 714 | fill_fsps_pcie_params, |
| 715 | fill_fsps_misc_power_params, |
| 716 | fill_fsps_ufs_params, |
| 717 | fill_fsps_ai_params, |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 718 | fill_fsps_irq_params, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 719 | }; |
| 720 | |
| 721 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 722 | fill_fsps_params[i](s_cfg, config); |
| 723 | } |
| 724 | |
| 725 | /* UPD parameters to be initialized before SiliconInit */ |
| 726 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 727 | { |
| 728 | struct soc_intel_meteorlake_config *config; |
| 729 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
| 730 | FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; |
| 731 | |
| 732 | config = config_of_soc(); |
| 733 | arch_silicon_init_params(s_arch_cfg); |
| 734 | soc_silicon_init_params(s_cfg, config); |
| 735 | mainboard_silicon_init_params(s_cfg); |
| 736 | } |
| 737 | |
| 738 | /* |
| 739 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 740 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 741 | * Phase | FSP return point | Purpose |
| 742 | * ------- + ------------------------------------------------ + ------------------------------- |
| 743 | * 1 | After TCSS initialization completed | for TCSS specific init |
Subrata Banik | f251a6a | 2022-12-11 16:39:05 +0530 | [diff] [blame] | 744 | * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 745 | */ |
| 746 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 747 | { |
| 748 | switch (phase_index) { |
| 749 | case 1: |
| 750 | /* TCSS specific initialization here */ |
| 751 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 752 | __FILE__, __func__); |
| 753 | |
| 754 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 755 | const config_t *config = config_of_soc(); |
| 756 | tcss_configure(config->typec_aux_bias_pads); |
| 757 | } |
| 758 | break; |
Subrata Banik | f251a6a | 2022-12-11 16:39:05 +0530 | [diff] [blame] | 759 | case 2: |
| 760 | /* CPU specific initialization here */ |
| 761 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 762 | __FILE__, __func__); |
| 763 | before_post_cpus_init(); |
| 764 | /* Enable BIOS Reset CPL */ |
| 765 | enable_bios_reset_cpl(); |
| 766 | break; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 767 | default: |
| 768 | break; |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | /* Mainboard GPIO Configuration */ |
| 773 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
| 774 | { |
| 775 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 776 | } |