Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <cbfs.h> |
| 5 | #include <console/console.h> |
| 6 | #include <cpu/intel/cpu_ids.h> |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 7 | #include <cpu/intel/microcode.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <fsp/api.h> |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 11 | #include <fsp/fsp_debug_event.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 12 | #include <fsp/ppi/mp_service_ppi.h> |
| 13 | #include <fsp/util.h> |
Dinesh Gehlot | e7c1f7d | 2022-12-06 10:58:48 +0000 | [diff] [blame] | 14 | #include <option.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 15 | #include <intelblocks/cse.h> |
| 16 | #include <intelblocks/lpss.h> |
Subrata Banik | f251a6a | 2022-12-11 16:39:05 +0530 | [diff] [blame] | 17 | #include <intelblocks/mp_init.h> |
| 18 | #include <intelblocks/systemagent.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 19 | #include <intelblocks/xdci.h> |
| 20 | #include <intelpch/lockdown.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 21 | #include <security/vboot/vboot_common.h> |
John Zhao | 54a03e4 | 2022-08-03 20:07:03 -0700 | [diff] [blame] | 22 | #include <soc/cpu.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 23 | #include <soc/gpio_soc_defs.h> |
| 24 | #include <soc/intel/common/vbt.h> |
| 25 | #include <soc/pci_devs.h> |
| 26 | #include <soc/pcie.h> |
| 27 | #include <soc/ramstage.h> |
| 28 | #include <soc/soc_chip.h> |
| 29 | #include <soc/soc_info.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 30 | #include <string.h> |
Dinesh Gehlot | e7c1f7d | 2022-12-06 10:58:48 +0000 | [diff] [blame] | 31 | #include <types.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 32 | |
| 33 | /* THC assignment definition */ |
| 34 | #define THC_NONE 0 |
| 35 | #define THC_0 1 |
| 36 | #define THC_1 2 |
| 37 | |
| 38 | /* SATA DEVSLP idle timeout default values */ |
| 39 | #define DEF_DMVAL 15 |
| 40 | #define DEF_DITOVAL 625 |
| 41 | |
| 42 | /* |
| 43 | * ME End of Post configuration |
| 44 | * 0 - Disable EOP. |
| 45 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 46 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 47 | */ |
| 48 | enum fsp_end_of_post { |
| 49 | EOP_DISABLE = 0, |
| 50 | EOP_PEI = 1, |
| 51 | EOP_DXE = 2, |
| 52 | }; |
| 53 | |
| 54 | static const pci_devfn_t i2c_dev[] = { |
| 55 | PCI_DEVFN_I2C0, |
| 56 | PCI_DEVFN_I2C1, |
| 57 | PCI_DEVFN_I2C2, |
| 58 | PCI_DEVFN_I2C3, |
| 59 | PCI_DEVFN_I2C4, |
| 60 | PCI_DEVFN_I2C5, |
| 61 | }; |
| 62 | |
| 63 | static const pci_devfn_t gspi_dev[] = { |
| 64 | PCI_DEVFN_GSPI0, |
| 65 | PCI_DEVFN_GSPI1, |
Angel Pons | c7c746c | 2022-07-16 12:37:38 +0200 | [diff] [blame] | 66 | PCI_DEVFN_GSPI2, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | static const pci_devfn_t uart_dev[] = { |
| 70 | PCI_DEVFN_UART0, |
| 71 | PCI_DEVFN_UART1, |
| 72 | PCI_DEVFN_UART2 |
| 73 | }; |
| 74 | |
| 75 | /* |
| 76 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 77 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 78 | * In order to ensure that mainboard setting does not disable L1 substates |
| 79 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 80 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 81 | * value is set in fsp_params. |
| 82 | * 0: Use FSP UPD default |
| 83 | * 1: Disable L1 substates |
| 84 | * 2: Use L1.1 |
| 85 | * 3: Use L1.2 (FSP UPD default) |
| 86 | */ |
| 87 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 88 | { |
Subrata Banik | ad6c407 | 2022-12-21 11:41:33 +0530 | [diff] [blame^] | 89 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) |
| 90 | ctl = L1_SS_DISABLED; |
| 91 | else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 92 | ctl = L1_SS_L1_2; |
| 93 | return ctl - 1; |
| 94 | } |
| 95 | |
| 96 | __weak void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) |
| 97 | { |
| 98 | /* Override settings per board. */ |
| 99 | } |
| 100 | |
| 101 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 102 | const struct soc_intel_meteorlake_config *config) |
| 103 | { |
| 104 | int max_port, i; |
| 105 | |
| 106 | max_port = get_max_i2c_port(); |
| 107 | for (i = 0; i < max_port; i++) { |
| 108 | s_cfg->SerialIoI2cMode[i] = is_devfn_enabled(i2c_dev[i]) ? |
| 109 | config->serial_io_i2c_mode[i] : 0; |
| 110 | } |
| 111 | |
| 112 | max_port = get_max_gspi_port(); |
| 113 | for (i = 0; i < max_port; i++) { |
| 114 | s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i]; |
| 115 | s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i]; |
| 116 | s_cfg->SerialIoSpiMode[i] = is_devfn_enabled(gspi_dev[i]) ? |
| 117 | config->serial_io_gspi_mode[i] : 0; |
| 118 | } |
| 119 | |
| 120 | max_port = get_max_uart_port(); |
| 121 | for (i = 0; i < max_port; i++) { |
| 122 | s_cfg->SerialIoUartMode[i] = is_devfn_enabled(uart_dev[i]) ? |
| 123 | config->serial_io_uart_mode[i] : 0; |
| 124 | } |
| 125 | } |
| 126 | |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 127 | static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 128 | const struct soc_intel_meteorlake_config *config) |
| 129 | { |
| 130 | const struct microcode *microcode_file; |
| 131 | size_t microcode_len; |
| 132 | |
| 133 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 134 | microcode_file = intel_microcode_find(); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 135 | |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 136 | if (microcode_file != NULL) { |
| 137 | microcode_len = get_microcode_size(microcode_file); |
| 138 | if (microcode_len != 0) { |
| 139 | /* Update CPU Microcode patch base address/size */ |
| 140 | s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; |
| 141 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
| 142 | } |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 143 | } |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 144 | } |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 145 | |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 146 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 147 | const struct soc_intel_meteorlake_config *config) |
| 148 | { |
Subrata Banik | 848c37d | 2022-12-09 13:38:26 +0530 | [diff] [blame] | 149 | /* |
| 150 | * FIXME: FSP assumes ownership of the APs (Application Processors) |
| 151 | * upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. |
| 152 | * Hence, pass a valid pointer to the CpuMpPpi UPD unconditionally. |
| 153 | * This would avoid APs from getting hijacked by FSP while coreboot |
| 154 | * decides to set SkipMpInit UPD. |
| 155 | */ |
| 156 | s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 157 | |
| 158 | /* |
| 159 | * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature |
| 160 | * programming. |
| 161 | */ |
| 162 | if (CONFIG(MTL_USE_FSP_MP_INIT)) |
Subrata Banik | 10929ef | 2022-12-09 13:31:47 +0530 | [diff] [blame] | 163 | fill_fsps_microcode_params(s_cfg, config); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | |
| 167 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 168 | const struct soc_intel_meteorlake_config *config) |
| 169 | { |
| 170 | /* Load VBT before devicetree-specific config. */ |
| 171 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 172 | |
| 173 | /* Check if IGD is present and fill Graphics init param accordingly */ |
| 174 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD); |
| 175 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Subrata Banik | 4cc8a6c | 2022-09-07 09:48:28 -0700 | [diff] [blame] | 176 | s_cfg->PavpEnable = CONFIG(PAVP); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 180 | const struct soc_intel_meteorlake_config *config) |
| 181 | { |
| 182 | const struct device *tcss_port_arr[] = { |
| 183 | DEV_PTR(tcss_usb3_port1), |
| 184 | DEV_PTR(tcss_usb3_port2), |
| 185 | DEV_PTR(tcss_usb3_port3), |
| 186 | DEV_PTR(tcss_usb3_port4), |
| 187 | }; |
| 188 | |
| 189 | s_cfg->TcssAuxOri = config->tcss_aux_ori; |
| 190 | |
| 191 | /* Explicitly clear this field to avoid using defaults */ |
| 192 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
| 193 | |
| 194 | /* D3Hot and D3Cold for TCSS */ |
| 195 | s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; |
| 196 | s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable; |
| 197 | s_cfg->UsbTcPortEn = 0; |
| 198 | |
| 199 | for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |
| 200 | if (is_dev_enabled(tcss_port_arr[i])) |
| 201 | s_cfg->UsbTcPortEn |= BIT(i); |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 206 | const struct soc_intel_meteorlake_config *config) |
| 207 | { |
| 208 | /* Chipset Lockdown */ |
| 209 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 210 | s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; |
| 211 | s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; |
| 212 | s_cfg->PchUnlockGpioPads = !lockdown_by_fsp; |
| 213 | s_cfg->RtcMemoryLock = lockdown_by_fsp; |
| 214 | s_cfg->SkipPamLock = !lockdown_by_fsp; |
| 215 | |
| 216 | /* coreboot will send EOP before loading payload */ |
| 217 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
| 218 | } |
| 219 | |
| 220 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 221 | const struct soc_intel_meteorlake_config *config) |
| 222 | { |
| 223 | int i, max_port; |
| 224 | |
| 225 | max_port = get_max_usb20_port(); |
| 226 | for (i = 0; i < max_port; i++) { |
| 227 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 228 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 229 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 230 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 231 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 232 | |
| 233 | if (config->usb2_ports[i].enable) |
| 234 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 235 | else |
| 236 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
| 237 | } |
| 238 | |
| 239 | max_port = get_max_usb30_port(); |
| 240 | for (i = 0; i < max_port; i++) { |
| 241 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 242 | if (config->usb3_ports[i].enable) |
| 243 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 244 | else |
| 245 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
| 246 | |
| 247 | if (config->usb3_ports[i].tx_de_emp) { |
| 248 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 249 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 250 | } |
| 251 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 252 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 253 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
| 254 | config->usb3_ports[i].tx_downscale_amp; |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | max_port = get_max_tcss_port(); |
| 259 | for (i = 0; i < max_port; i++) { |
| 260 | s_cfg->PortUsb30Enable[i] = config->tcss_ports[i].enable; |
| 261 | if (config->tcss_ports[i].enable) |
| 262 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 267 | const struct soc_intel_meteorlake_config *config) |
| 268 | { |
| 269 | s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG); |
| 270 | } |
| 271 | |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 272 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 273 | const struct soc_intel_meteorlake_config *config) |
| 274 | { |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 275 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 276 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
| 277 | } |
| 278 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 279 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 280 | const struct soc_intel_meteorlake_config *config) |
| 281 | { |
| 282 | /* SATA */ |
| 283 | s_cfg->SataEnable = is_devfn_enabled(PCI_DEVFN_SATA); |
| 284 | if (s_cfg->SataEnable) { |
| 285 | s_cfg->SataMode = config->sata_mode; |
| 286 | s_cfg->SataSalpSupport = config->sata_salp_support; |
| 287 | memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable, |
| 288 | sizeof(s_cfg->SataPortsEnable)); |
| 289 | memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp, |
| 290 | sizeof(s_cfg->SataPortsDevSlp)); |
| 291 | } |
| 292 | |
| 293 | /* |
| 294 | * Power Optimizer for SATA. |
| 295 | * SataPwrOptimizeDisable is default to 0. |
| 296 | * Boards not needing the optimizers explicitly disables them by setting |
| 297 | * these disable variables to 1 in devicetree overrides. |
| 298 | */ |
| 299 | s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable); |
| 300 | /* |
| 301 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 302 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 303 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 304 | * The default values can be changed from devicetree. |
| 305 | */ |
| 306 | for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) { |
| 307 | if (config->sata_ports_enable_dito_config[i]) { |
| 308 | s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i]; |
| 309 | s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i]; |
| 310 | } |
| 311 | } |
| 312 | } |
| 313 | |
| 314 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 315 | const struct soc_intel_meteorlake_config *config) |
| 316 | { |
| 317 | /* Enable TCPU for processor thermal control */ |
| 318 | s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF); |
| 319 | |
| 320 | /* Set TccActivationOffset */ |
| 321 | s_cfg->TccActivationOffset = config->tcc_offset; |
| 322 | } |
| 323 | |
| 324 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 325 | const struct soc_intel_meteorlake_config *config) |
| 326 | { |
| 327 | /* LAN */ |
| 328 | s_cfg->PchLanEnable = is_devfn_enabled(PCI_DEVFN_GBE); |
| 329 | } |
| 330 | |
| 331 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 332 | const struct soc_intel_meteorlake_config *config) |
| 333 | { |
| 334 | /* CNVi */ |
| 335 | s_cfg->CnviMode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI); |
| 336 | s_cfg->CnviBtCore = config->cnvi_bt_core; |
| 337 | s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; |
| 338 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
| 339 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
| 340 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
| 341 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
| 342 | } |
| 343 | |
| 344 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 345 | const struct soc_intel_meteorlake_config *config) |
| 346 | { |
| 347 | /* VMD */ |
| 348 | s_cfg->VmdEnable = is_devfn_enabled(PCI_DEVFN_VMD); |
| 349 | } |
| 350 | |
| 351 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 352 | const struct soc_intel_meteorlake_config *config) |
| 353 | { |
Sridhar Siricilla | cb4d464 | 2022-09-26 12:12:20 +0530 | [diff] [blame] | 354 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
| 355 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(PCI_DEVFN_TBT(i)); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 356 | } |
| 357 | |
| 358 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 359 | const struct soc_intel_meteorlake_config *config) |
| 360 | { |
| 361 | /* Legacy 8254 timer support */ |
Dinesh Gehlot | e7c1f7d | 2022-12-06 10:58:48 +0000 | [diff] [blame] | 362 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 363 | s_cfg->Enable8254ClockGating = !use_8254; |
| 364 | s_cfg->Enable8254ClockGatingOnS3 = !use_8254; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 365 | } |
| 366 | |
Kapil Porwal | 89ea312 | 2022-11-15 19:06:49 +0530 | [diff] [blame] | 367 | static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, |
| 368 | const struct soc_intel_meteorlake_config *config) |
| 369 | { |
| 370 | /* |
| 371 | * Legacy PM ACPI Timer (and TCO Timer) |
| 372 | * This *must* be 1 in any case to keep FSP from |
| 373 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 374 | * 2) disabling the PM ACPI Timer. |
| 375 | * We handle both by ourself! |
| 376 | */ |
| 377 | s_cfg->EnableTcoTimer = 1; |
| 378 | } |
| 379 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 380 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 381 | const struct soc_intel_meteorlake_config *config) |
| 382 | { |
| 383 | int max_port = get_max_pcie_port(); |
| 384 | uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table()); |
| 385 | for (int i = 0; i < max_port; i++) { |
| 386 | if (!(enable_mask & BIT(i))) |
| 387 | continue; |
| 388 | const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i]; |
| 389 | s_cfg->PcieRpL1Substates[i] = |
| 390 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
| 391 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 392 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 393 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) |
| 394 | || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 395 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
| 396 | } |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 397 | s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 398 | } |
| 399 | |
| 400 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 401 | const struct soc_intel_meteorlake_config *config) |
| 402 | { |
Kapil Porwal | 66e44e3 | 2022-11-16 10:19:17 +0530 | [diff] [blame] | 403 | /* Skip setting D0I3 bit for all HECI devices */ |
| 404 | s_cfg->DisableD0I3SettingForHeci = 1; |
| 405 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 406 | s_cfg->Hwp = 1; |
| 407 | s_cfg->Cx = 1; |
| 408 | s_cfg->PsOnEnable = 1; |
| 409 | /* Enable the energy efficient turbo mode */ |
| 410 | s_cfg->EnergyEfficientTurbo = 1; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 411 | s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); |
| 412 | } |
| 413 | |
| 414 | |
| 415 | static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg, |
| 416 | const struct soc_intel_meteorlake_config *config) |
| 417 | { |
| 418 | s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS); |
| 419 | } |
| 420 | |
| 421 | static void fill_fsps_ai_params(FSP_S_CONFIG *s_cfg, |
| 422 | const struct soc_intel_meteorlake_config *config) |
| 423 | { |
| 424 | s_cfg->GnaEnable = is_devfn_enabled(PCI_DEVFN_GNA); |
Srinidhi N Kaushik | 9f6e25d | 2022-08-08 20:38:19 -0700 | [diff] [blame] | 425 | s_cfg->VpuEnable = is_devfn_enabled(PCI_DEVFN_VPU); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) |
| 429 | { |
zhaojohn | 9f5fea9 | 2022-09-20 08:12:47 -0700 | [diff] [blame] | 430 | /* |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 431 | * EnableMultiPhaseSiliconInit for running MultiPhaseSiInit |
| 432 | */ |
zhaojohn | 9f5fea9 | 2022-09-20 08:12:47 -0700 | [diff] [blame] | 433 | s_arch_cfg->EnableMultiPhaseSiliconInit = 1; |
Srinidhi N Kaushik | 9a69002 | 2022-07-25 22:12:34 -0700 | [diff] [blame] | 434 | |
| 435 | /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ |
| 436 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && |
| 437 | CONFIG(FSP_ENABLE_SERIAL_DEBUG)) |
| 438 | s_arch_cfg->FspEventHandler = (FSP_EVENT_HANDLER) |
| 439 | fsp_debug_event_handler; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 443 | struct soc_intel_meteorlake_config *config) |
| 444 | { |
| 445 | /* Override settings per board if required. */ |
| 446 | mainboard_update_soc_chip_config(config); |
| 447 | |
Arthur Heymans | 4081d6c | 2022-07-29 10:45:52 +0200 | [diff] [blame] | 448 | void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 449 | const struct soc_intel_meteorlake_config *config) = { |
| 450 | fill_fsps_lpss_params, |
| 451 | fill_fsps_cpu_params, |
| 452 | fill_fsps_igd_params, |
| 453 | fill_fsps_tcss_params, |
| 454 | fill_fsps_chipset_lockdown_params, |
| 455 | fill_fsps_xhci_params, |
| 456 | fill_fsps_xdci_params, |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 457 | fill_fsps_uart_params, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 458 | fill_fsps_sata_params, |
| 459 | fill_fsps_thermal_params, |
| 460 | fill_fsps_lan_params, |
| 461 | fill_fsps_cnvi_params, |
| 462 | fill_fsps_vmd_params, |
| 463 | fill_fsps_tbt_params, |
| 464 | fill_fsps_8254_params, |
Kapil Porwal | 89ea312 | 2022-11-15 19:06:49 +0530 | [diff] [blame] | 465 | fill_fsps_pm_timer_params, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 466 | fill_fsps_pcie_params, |
| 467 | fill_fsps_misc_power_params, |
| 468 | fill_fsps_ufs_params, |
| 469 | fill_fsps_ai_params, |
| 470 | }; |
| 471 | |
| 472 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 473 | fill_fsps_params[i](s_cfg, config); |
| 474 | } |
| 475 | |
| 476 | /* UPD parameters to be initialized before SiliconInit */ |
| 477 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 478 | { |
| 479 | struct soc_intel_meteorlake_config *config; |
| 480 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
| 481 | FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; |
| 482 | |
| 483 | config = config_of_soc(); |
| 484 | arch_silicon_init_params(s_arch_cfg); |
| 485 | soc_silicon_init_params(s_cfg, config); |
| 486 | mainboard_silicon_init_params(s_cfg); |
| 487 | } |
| 488 | |
| 489 | /* |
| 490 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 491 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 492 | * Phase | FSP return point | Purpose |
| 493 | * ------- + ------------------------------------------------ + ------------------------------- |
| 494 | * 1 | After TCSS initialization completed | for TCSS specific init |
Subrata Banik | f251a6a | 2022-12-11 16:39:05 +0530 | [diff] [blame] | 495 | * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 496 | */ |
| 497 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 498 | { |
| 499 | switch (phase_index) { |
| 500 | case 1: |
| 501 | /* TCSS specific initialization here */ |
| 502 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 503 | __FILE__, __func__); |
| 504 | |
| 505 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 506 | const config_t *config = config_of_soc(); |
| 507 | tcss_configure(config->typec_aux_bias_pads); |
| 508 | } |
| 509 | break; |
Subrata Banik | f251a6a | 2022-12-11 16:39:05 +0530 | [diff] [blame] | 510 | case 2: |
| 511 | /* CPU specific initialization here */ |
| 512 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 513 | __FILE__, __func__); |
| 514 | before_post_cpus_init(); |
| 515 | /* Enable BIOS Reset CPL */ |
| 516 | enable_bios_reset_cpl(); |
| 517 | break; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 518 | default: |
| 519 | break; |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | /* Mainboard GPIO Configuration */ |
| 524 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
| 525 | { |
| 526 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 527 | } |