Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 3 | #include <assert.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
| 6 | #include <cpu/intel/common/common.h> |
| 7 | #include <cpu/intel/smm_reloc.h> |
| 8 | #include <cpu/intel/turbo.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 9 | #include <cpu/x86/lapic.h> |
| 10 | #include <cpu/x86/mp.h> |
| 11 | #include <cpu/x86/msr.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 12 | #include <device/pci.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 13 | #include <fsp/api.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 14 | #include <intelblocks/acpi.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 15 | #include <intelblocks/cpulib.h> |
| 16 | #include <intelblocks/mp_init.h> |
| 17 | #include <intelblocks/msr.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 18 | #include <soc/cpu.h> |
| 19 | #include <soc/msr.h> |
| 20 | #include <soc/pci_devs.h> |
| 21 | #include <soc/soc_chip.h> |
| 22 | #include <soc/soc_info.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 23 | |
| 24 | bool cpu_soc_is_in_untrusted_mode(void) |
| 25 | { |
| 26 | msr_t msr; |
| 27 | |
| 28 | msr = rdmsr(MSR_BIOS_DONE); |
| 29 | return !!(msr.lo & ENABLE_IA_UNTRUSTED); |
| 30 | } |
| 31 | |
Subrata Banik | 85e619c | 2022-12-05 20:52:38 +0530 | [diff] [blame] | 32 | void cpu_soc_bios_done(void) |
| 33 | { |
| 34 | msr_t msr; |
| 35 | |
| 36 | msr = rdmsr(MSR_BIOS_DONE); |
| 37 | msr.lo |= ENABLE_IA_UNTRUSTED; |
| 38 | wrmsr(MSR_BIOS_DONE, msr); |
| 39 | } |
| 40 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 41 | uint8_t get_supported_lpm_mask(void) |
| 42 | { |
| 43 | return LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2; |
| 44 | } |
| 45 | |
| 46 | static void soc_fsp_load(void) |
| 47 | { |
| 48 | fsps_load(); |
| 49 | } |
| 50 | |
| 51 | static void configure_misc(void) |
| 52 | { |
| 53 | msr_t msr; |
| 54 | |
| 55 | config_t *conf = (config_t *)config_of_soc(); |
| 56 | |
| 57 | msr = rdmsr(IA32_MISC_ENABLE); |
| 58 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 59 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| 60 | wrmsr(IA32_MISC_ENABLE, msr); |
| 61 | |
| 62 | /* Set EIST status */ |
| 63 | cpu_set_eist(conf->eist_enable); |
| 64 | |
| 65 | /* Disable Thermal interrupts */ |
| 66 | msr.lo = 0; |
| 67 | msr.hi = 0; |
| 68 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 69 | |
| 70 | /* Enable package critical interrupt only */ |
| 71 | msr.lo = 1 << 4; |
| 72 | msr.hi = 0; |
| 73 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 74 | |
| 75 | /* Enable PROCHOT */ |
| 76 | msr = rdmsr(MSR_POWER_CTL); |
| 77 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ |
| 78 | msr.lo |= (1 << 23); /* Lock it */ |
| 79 | wrmsr(MSR_POWER_CTL, msr); |
| 80 | } |
| 81 | |
| 82 | enum core_type get_soc_cpu_type(void) |
| 83 | { |
| 84 | if (cpu_is_hybrid_supported()) |
| 85 | return cpu_get_cpu_type(); |
| 86 | else |
| 87 | return CPUID_CORE_TYPE_INTEL_CORE; |
| 88 | } |
| 89 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 90 | bool soc_is_nominal_freq_supported(void) |
| 91 | { |
| 92 | return true; |
| 93 | } |
| 94 | |
Subrata Banik | e96993d | 2022-07-09 22:06:45 +0000 | [diff] [blame] | 95 | static void enable_x2apic(void) |
| 96 | { |
| 97 | if (!CONFIG(X2APIC_LATE_WORKAROUND)) |
| 98 | return; |
| 99 | |
| 100 | enable_lapic_mode(true); |
| 101 | } |
| 102 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 103 | /* All CPUs including BSP will run the following function. */ |
| 104 | void soc_core_init(struct device *cpu) |
| 105 | { |
| 106 | /* Clear out pending MCEs */ |
| 107 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 108 | * of these banks are core vs package scope. For now every CPU clears |
| 109 | * every bank. */ |
| 110 | mca_configure(); |
| 111 | |
Subrata Banik | e96993d | 2022-07-09 22:06:45 +0000 | [diff] [blame] | 112 | enable_x2apic(); |
| 113 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 114 | enable_lapic_tpr(); |
| 115 | |
| 116 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 117 | configure_misc(); |
| 118 | |
| 119 | enable_pm_timer_emulation(); |
| 120 | |
| 121 | /* Enable Direct Cache Access */ |
| 122 | configure_dca_cap(); |
| 123 | |
| 124 | /* Set energy policy */ |
| 125 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 126 | |
| 127 | /* Enable Turbo */ |
| 128 | enable_turbo(); |
Tarun Tuli | 24a0547 | 2022-08-22 16:41:35 -0400 | [diff] [blame] | 129 | |
| 130 | if (CONFIG(INTEL_TME) && is_tme_supported()) |
| 131 | set_tme_core_activate(); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | static void per_cpu_smm_trigger(void) |
| 135 | { |
| 136 | /* Relocate the SMM handler. */ |
| 137 | smm_relocate(); |
| 138 | } |
| 139 | |
| 140 | static void post_mp_init(void) |
| 141 | { |
| 142 | /* Set Max Ratio */ |
| 143 | cpu_set_max_ratio(); |
| 144 | |
| 145 | /* |
| 146 | * 1. Now that all APs have been relocated as well as the BSP let SMIs |
| 147 | * start flowing. |
| 148 | * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT |
| 149 | * to avoid shutdown hang due to lack of init on certain IP in FSP-S. |
| 150 | */ |
| 151 | global_smi_enable_no_pwrbtn(); |
| 152 | } |
| 153 | |
| 154 | static const struct mp_ops mp_ops = { |
| 155 | /* |
| 156 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 157 | * that are set prior to ramstage. |
| 158 | * Real MTRRs programming are being done after resource allocation. |
| 159 | */ |
| 160 | .pre_mp_init = soc_fsp_load, |
| 161 | .get_cpu_count = get_cpu_count, |
| 162 | .get_smm_info = smm_info, |
| 163 | .get_microcode_info = get_microcode_info, |
| 164 | .pre_mp_smm_init = smm_initialize, |
| 165 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 166 | .relocation_handler = smm_relocation_handler, |
| 167 | .post_mp_init = post_mp_init, |
| 168 | }; |
| 169 | |
| 170 | void soc_init_cpus(struct bus *cpu_bus) |
| 171 | { |
| 172 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 173 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 174 | |
| 175 | /* Thermal throttle activation offset */ |
| 176 | configure_tcc_thermal_target(); |
| 177 | } |