Elyes HAOUAS | d72155d | 2020-05-07 07:51:34 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 2 | |
Martin Roth | effaf8f | 2019-10-20 20:29:22 -0600 | [diff] [blame] | 3 | /* This came from the Linux kernel (include/linux/usb/ehci_def.h). */ |
| 4 | |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 5 | #ifndef EHCI_H |
| 6 | #define EHCI_H |
| 7 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 8 | /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 9 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 10 | /* Section 2.2 Host Controller Capability Registers */ |
| 11 | struct ehci_caps { |
| 12 | /* these fields are specified as 8 and 16 bit registers, |
| 13 | * but some hosts can't perform 8 or 16 bit PCI accesses. |
| 14 | */ |
| 15 | u32 hc_capbase; |
| 16 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ |
| 17 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ |
| 18 | u32 hcs_params; /* HCSPARAMS - offset 0x4 */ |
| 19 | #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ |
| 20 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ |
| 21 | #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ |
| 22 | #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ |
| 23 | #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ |
| 24 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ |
| 25 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ |
| 26 | |
| 27 | u32 hcc_params; /* HCCPARAMS - offset 0x8 */ |
| 28 | /* EHCI 1.1 addendum */ |
| 29 | #define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19)) |
| 30 | #define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18)) |
| 31 | #define HCC_LPM(p) ((p)&(1 << 17)) |
| 32 | #define HCC_HW_PREFETCH(p) ((p)&(1 << 16)) |
| 33 | |
| 34 | #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 35 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ |
| 36 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 37 | #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 38 | #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ |
| 39 | #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 40 | u8 portroute[8]; /* nibbles for routing - offset 0xC */ |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 41 | } __packed; |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 42 | |
| 43 | /* Section 2.3 Host Controller Operational Registers */ |
| 44 | struct ehci_regs { |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 45 | /* USBCMD: offset 0x00 */ |
| 46 | u32 command; |
| 47 | |
| 48 | /* EHCI 1.1 addendum */ |
| 49 | #define CMD_HIRD (0xf<<24) /* host initiated resume duration */ |
| 50 | #define CMD_PPCEE (1<<15) /* per port change event enable */ |
| 51 | #define CMD_FSP (1<<14) /* fully synchronized prefetch */ |
| 52 | #define CMD_ASPE (1<<13) /* async schedule prefetch enable */ |
| 53 | #define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 54 | /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 55 | #define CMD_PARK (1<<11) /* enable "park" on async qh */ |
| 56 | #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ |
| 57 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ |
| 58 | #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ |
| 59 | #define CMD_ASE (1<<5) /* async schedule enable */ |
| 60 | #define CMD_PSE (1<<4) /* periodic schedule enable */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 61 | /* 3:2 is periodic frame list size */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 62 | #define CMD_RESET (1<<1) /* reset HC not bus */ |
| 63 | #define CMD_RUN (1<<0) /* start/stop HC */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 64 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 65 | /* USBSTS: offset 0x04 */ |
| 66 | u32 status; |
| 67 | #define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */ |
| 68 | #define STS_ASS (1<<15) /* Async Schedule Status */ |
| 69 | #define STS_PSS (1<<14) /* Periodic Schedule Status */ |
| 70 | #define STS_RECL (1<<13) /* Reclamation */ |
| 71 | #define STS_HALT (1<<12) /* Not running (any reason) */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 72 | /* some bits reserved */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 73 | /* these STS_* flags are also intr_enable bits (USBINTR) */ |
| 74 | #define STS_IAA (1<<5) /* Interrupted on async advance */ |
| 75 | #define STS_FATAL (1<<4) /* such as some PCI access errors */ |
| 76 | #define STS_FLR (1<<3) /* frame list rolled over */ |
| 77 | #define STS_PCD (1<<2) /* port change detect */ |
| 78 | #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ |
| 79 | #define STS_INT (1<<0) /* "normal" completion (short, ...) */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 80 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 81 | /* USBINTR: offset 0x08 */ |
| 82 | u32 intr_enable; |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 83 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 84 | /* FRINDEX: offset 0x0C */ |
| 85 | u32 frame_index; /* current microframe number */ |
| 86 | /* CTRLDSSEGMENT: offset 0x10 */ |
| 87 | u32 segment; /* address bits 63:32 if needed */ |
| 88 | /* PERIODICLISTBASE: offset 0x14 */ |
| 89 | u32 frame_list; /* points to periodic list */ |
| 90 | /* ASYNCLISTADDR: offset 0x18 */ |
| 91 | u32 async_next; /* address of next async queue head */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 92 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 93 | u32 reserved[9]; |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 94 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 95 | /* CONFIGFLAG: offset 0x40 */ |
| 96 | u32 configured_flag; |
| 97 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 98 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 99 | /* PORTSC: offset 0x44 */ |
| 100 | u32 port_status[0]; /* up to N_PORTS */ |
| 101 | /* EHCI 1.1 addendum */ |
| 102 | #define PORTSC_SUSPEND_STS_ACK 0 |
| 103 | #define PORTSC_SUSPEND_STS_NYET 1 |
| 104 | #define PORTSC_SUSPEND_STS_STALL 2 |
| 105 | #define PORTSC_SUSPEND_STS_ERR 3 |
| 106 | |
| 107 | #define PORT_DEV_ADDR (0x7f<<25) /* device address */ |
| 108 | #define PORT_SSTS (0x3<<23) /* suspend status */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 109 | /* 31:23 reserved */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 110 | #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ |
| 111 | #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ |
| 112 | #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 113 | /* 19:16 for port testing */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 114 | #define PORT_TEST_PKT (0x4<<16) /* Port Test Control - packet test */ |
| 115 | #define PORT_LED_OFF (0<<14) |
| 116 | #define PORT_LED_AMBER (1<<14) |
| 117 | #define PORT_LED_GREEN (2<<14) |
| 118 | #define PORT_LED_MASK (3<<14) |
| 119 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ |
| 120 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ |
| 121 | #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 122 | /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ |
| 123 | /* 9 reserved */ |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 124 | #define PORT_LPM (1<<9) /* LPM transaction */ |
| 125 | #define PORT_RESET (1<<8) /* reset port */ |
| 126 | #define PORT_SUSPEND (1<<7) /* suspend port */ |
| 127 | #define PORT_RESUME (1<<6) /* resume it */ |
| 128 | #define PORT_OCC (1<<5) /* over current change */ |
| 129 | #define PORT_OC (1<<4) /* over current active */ |
| 130 | #define PORT_PEC (1<<3) /* port enable change */ |
| 131 | #define PORT_PE (1<<2) /* port enable */ |
| 132 | #define PORT_CSC (1<<1) /* connect status change */ |
| 133 | #define PORT_CONNECT (1<<0) /* device connected */ |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 134 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 135 | } __packed; |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 136 | |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 137 | #define USBMODE 0x68 /* USB Device mode */ |
| 138 | #define USBMODE_SDIS (1<<3) /* Stream disable */ |
| 139 | #define USBMODE_BE (1<<2) /* BE/LE endianness select */ |
| 140 | #define USBMODE_CM_HC (3<<0) /* host controller mode */ |
| 141 | #define USBMODE_CM_IDLE (0<<0) /* idle state */ |
| 142 | |
| 143 | /* Moorestown has some non-standard registers, partially due to the fact that |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 144 | * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 145 | * PORTSCx |
| 146 | */ |
| 147 | #define HOSTPC0 0x84 /* HOSTPC extension */ |
| 148 | #define HOSTPC_PHCD (1<<22) /* Phy clock disable */ |
| 149 | #define HOSTPC_PSPD (3<<25) /* Port speed detection */ |
| 150 | #define USBMODE_EX 0xc8 /* USB Device mode extension */ |
| 151 | #define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */ |
| 152 | #define USBMODE_EX_HC (3<<0) /* host controller mode */ |
| 153 | #define TXFILLTUNING 0x24 /* TX FIFO Tuning register */ |
| 154 | #define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */ |
| 155 | |
Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame] | 156 | /* Appendix C, Debug port ... intended for use with special "debug devices" |
| 157 | * that can help if there's no serial console. (nonstandard enumeration.) |
| 158 | */ |
| 159 | struct ehci_dbg_port { |
Uwe Hermann | 06694a8 | 2010-09-23 18:16:46 +0000 | [diff] [blame] | 160 | u32 control; |
| 161 | #define DBGP_OWNER (1<<30) |
| 162 | #define DBGP_ENABLED (1<<28) |
| 163 | #define DBGP_DONE (1<<16) |
| 164 | #define DBGP_INUSE (1<<10) |
| 165 | #define DBGP_ERRCODE(x) (((x)>>7)&0x07) |
| 166 | # define DBGP_ERR_BAD 1 |
| 167 | # define DBGP_ERR_SIGNAL 2 |
| 168 | #define DBGP_ERROR (1<<6) |
| 169 | #define DBGP_GO (1<<5) |
| 170 | #define DBGP_OUT (1<<4) |
| 171 | #define DBGP_LEN(x) (((x)>>0)&0x0f) |
| 172 | u32 pids; |
| 173 | #define DBGP_PID_GET(x) (((x)>>16)&0xff) |
| 174 | #define DBGP_PID_SET(data, tok) (((data)<<8)|(tok)) |
| 175 | u32 data03; |
| 176 | u32 data47; |
| 177 | u32 address; |
| 178 | #define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 179 | } __packed; |
Kyösti Mälkki | 83fe6d7 | 2014-02-25 20:11:52 +0200 | [diff] [blame] | 180 | |
| 181 | #define USB_DEBUG_DEVNUM 127 |
| 182 | |
Sven Schnelle | 20fc631 | 2011-10-30 09:57:35 +0100 | [diff] [blame] | 183 | #endif |