Yinghai Lu | d57241f | 2007-02-28 11:17:02 +0000 | [diff] [blame^] | 1 | #ifndef EHCI_H |
| 2 | #define EHCI_H |
| 3 | |
| 4 | struct ehci_caps { |
| 5 | /* these fields are specified as 8 and 16 bit registers, |
| 6 | * but some hosts can't perform 8 or 16 bit PCI accesses. |
| 7 | */ |
| 8 | u32 hc_capbase; |
| 9 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ |
| 10 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ |
| 11 | u32 hcs_params; /* HCSPARAMS - offset 0x4 */ |
| 12 | #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ |
| 13 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ |
| 14 | #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ |
| 15 | #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ |
| 16 | #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ |
| 17 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ |
| 18 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ |
| 19 | |
| 20 | u32 hcc_params; /* HCCPARAMS - offset 0x8 */ |
| 21 | #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ |
| 22 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ |
| 23 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ |
| 24 | #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ |
| 25 | #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ |
| 26 | #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ |
| 27 | u8 portroute [8]; /* nibbles for routing - offset 0xC */ |
| 28 | } __attribute__ ((packed)); |
| 29 | |
| 30 | /* Section 2.3 Host Controller Operational Registers */ |
| 31 | struct ehci_regs { |
| 32 | |
| 33 | /* USBCMD: offset 0x00 */ |
| 34 | u32 command; |
| 35 | /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ |
| 36 | #define CMD_PARK (1<<11) /* enable "park" on async qh */ |
| 37 | #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ |
| 38 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ |
| 39 | #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ |
| 40 | #define CMD_ASE (1<<5) /* async schedule enable */ |
| 41 | #define CMD_PSE (1<<4) /* periodic schedule enable */ |
| 42 | /* 3:2 is periodic frame list size */ |
| 43 | #define CMD_RESET (1<<1) /* reset HC not bus */ |
| 44 | #define CMD_RUN (1<<0) /* start/stop HC */ |
| 45 | |
| 46 | /* USBSTS: offset 0x04 */ |
| 47 | u32 status; |
| 48 | #define STS_ASS (1<<15) /* Async Schedule Status */ |
| 49 | #define STS_PSS (1<<14) /* Periodic Schedule Status */ |
| 50 | #define STS_RECL (1<<13) /* Reclamation */ |
| 51 | #define STS_HALT (1<<12) /* Not running (any reason) */ |
| 52 | /* some bits reserved */ |
| 53 | /* these STS_* flags are also intr_enable bits (USBINTR) */ |
| 54 | #define STS_IAA (1<<5) /* Interrupted on async advance */ |
| 55 | #define STS_FATAL (1<<4) /* such as some PCI access errors */ |
| 56 | #define STS_FLR (1<<3) /* frame list rolled over */ |
| 57 | #define STS_PCD (1<<2) /* port change detect */ |
| 58 | #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ |
| 59 | #define STS_INT (1<<0) /* "normal" completion (short, ...) */ |
| 60 | |
| 61 | /* USBINTR: offset 0x08 */ |
| 62 | u32 intr_enable; |
| 63 | |
| 64 | /* FRINDEX: offset 0x0C */ |
| 65 | u32 frame_index; /* current microframe number */ |
| 66 | /* CTRLDSSEGMENT: offset 0x10 */ |
| 67 | u32 segment; /* address bits 63:32 if needed */ |
| 68 | /* PERIODICLISTBASE: offset 0x14 */ |
| 69 | u32 frame_list; /* points to periodic list */ |
| 70 | /* ASYNCLISTADDR: offset 0x18 */ |
| 71 | u32 async_next; /* address of next async queue head */ |
| 72 | |
| 73 | u32 reserved [9]; |
| 74 | |
| 75 | /* CONFIGFLAG: offset 0x40 */ |
| 76 | u32 configured_flag; |
| 77 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ |
| 78 | |
| 79 | /* PORTSC: offset 0x44 */ |
| 80 | u32 port_status [0]; /* up to N_PORTS */ |
| 81 | /* 31:23 reserved */ |
| 82 | #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ |
| 83 | #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ |
| 84 | #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ |
| 85 | /* 19:16 for port testing */ |
| 86 | #define PORT_LED_OFF (0<<14) |
| 87 | #define PORT_LED_AMBER (1<<14) |
| 88 | #define PORT_LED_GREEN (2<<14) |
| 89 | #define PORT_LED_MASK (3<<14) |
| 90 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ |
| 91 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ |
| 92 | #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ |
| 93 | /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ |
| 94 | /* 9 reserved */ |
| 95 | #define PORT_RESET (1<<8) /* reset port */ |
| 96 | #define PORT_SUSPEND (1<<7) /* suspend port */ |
| 97 | #define PORT_RESUME (1<<6) /* resume it */ |
| 98 | #define PORT_OCC (1<<5) /* over current change */ |
| 99 | #define PORT_OC (1<<4) /* over current active */ |
| 100 | #define PORT_PEC (1<<3) /* port enable change */ |
| 101 | #define PORT_PE (1<<2) /* port enable */ |
| 102 | #define PORT_CSC (1<<1) /* connect status change */ |
| 103 | #define PORT_CONNECT (1<<0) /* device connected */ |
| 104 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) |
| 105 | } __attribute__ ((packed)); |
| 106 | |
| 107 | /* Appendix C, Debug port ... intended for use with special "debug devices" |
| 108 | * that can help if there's no serial console. (nonstandard enumeration.) |
| 109 | */ |
| 110 | struct ehci_dbg_port { |
| 111 | u32 control; |
| 112 | #define DBGP_OWNER (1<<30) |
| 113 | #define DBGP_ENABLED (1<<28) |
| 114 | #define DBGP_DONE (1<<16) |
| 115 | #define DBGP_INUSE (1<<10) |
| 116 | #define DBGP_ERRCODE(x) (((x)>>7)&0x07) |
| 117 | # define DBGP_ERR_BAD 1 |
| 118 | # define DBGP_ERR_SIGNAL 2 |
| 119 | #define DBGP_ERROR (1<<6) |
| 120 | #define DBGP_GO (1<<5) |
| 121 | #define DBGP_OUT (1<<4) |
| 122 | #define DBGP_LEN(x) (((x)>>0)&0x0f) |
| 123 | u32 pids; |
| 124 | #define DBGP_PID_GET(x) (((x)>>16)&0xff) |
| 125 | #define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) |
| 126 | u32 data03; |
| 127 | u32 data47; |
| 128 | u32 address; |
| 129 | #define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) |
| 130 | } __attribute__ ((packed)); |
| 131 | |
| 132 | #endif |