Ronald G. Minnich | cbc95f3 | 2007-09-09 19:43:31 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Ronald G. Minnich | cbc95f3 | 2007-09-09 19:43:31 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 20 | #include <stdint.h> |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 21 | #include <stdlib.h> |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 22 | #include <spd.h> |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 23 | #include <device/pci_def.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <device/pnp_def.h> |
| 26 | #include <arch/romcc_io.h> |
| 27 | #include <arch/hlt.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 28 | #include <console/console.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 29 | #include <lib.h> |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 30 | #include "cpu/x86/bist.h" |
| 31 | #include "cpu/x86/msr.h" |
| 32 | #include <cpu/amd/lxdef.h> |
| 33 | #include <cpu/amd/geode_post_code.h> |
| 34 | #include "southbridge/amd/cs5536/cs5536.h" |
| 35 | |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 36 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 37 | |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 38 | /* The ALIX1.C has no SMBus; the setup is hard-wired. */ |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 39 | static void cs5536_enable_smbus(void) { } |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 40 | |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 41 | #include "southbridge/amd/cs5536/cs5536_early_setup.c" |
| 42 | #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| 43 | |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 44 | /* The part is a Hynix hy5du121622ctp-d43. |
| 45 | * |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 46 | * HY 5D U 12 16 2 2 C <blank> T <blank> P D43 |
| 47 | * Hynix |
| 48 | * DDR SDRAM (5D) |
| 49 | * VDD 2.5 VDDQ 2.5 (U) |
| 50 | * 512M 8K REFRESH (12) |
| 51 | * x16 (16) |
| 52 | * 4banks (2) |
| 53 | * SSTL_2 (2) |
| 54 | * 4th GEN die (C) |
| 55 | * Normal Power Consumption (<blank> ) |
| 56 | * TSOP (T) |
| 57 | * Single Die (<blank>) |
| 58 | * Lead Free (P) |
| 59 | * DDR400 3-3-3 (D43) |
| 60 | */ |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 61 | /* SPD array */ |
| 62 | static const u8 spdbytes[] = { |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 63 | [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, |
| 64 | [SPD_BANK_DENSITY] = 0x40, |
| 65 | [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, |
| 66 | [SPD_MEMORY_TYPE] = 7, |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 67 | [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ |
| 68 | [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 69 | [SPD_NUM_BANKS_PER_SDRAM] = 4, |
| 70 | [SPD_PRIMARY_SDRAM_WIDTH] = 8, |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 71 | [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 72 | [SPD_NUM_COLUMNS] = 0xa, |
| 73 | [SPD_NUM_ROWS] = 3, |
| 74 | [SPD_REFRESH] = 0x3a, |
| 75 | [SPD_SDRAM_CYCLE_TIME_2ND] = 60, |
| 76 | [SPD_SDRAM_CYCLE_TIME_3RD] = 75, |
| 77 | [SPD_tRAS] = 40, |
| 78 | [SPD_tRCD] = 15, |
| 79 | [SPD_tRFC] = 70, |
| 80 | [SPD_tRP] = 15, |
| 81 | [SPD_tRRD] = 10, |
| 82 | }; |
| 83 | |
Ronald G. Minnich | 9d5c3a8 | 2007-11-01 15:15:14 +0000 | [diff] [blame] | 84 | static u8 spd_read_byte(u8 device, u8 address) |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 85 | { |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 86 | print_debug("spd_read_byte dev "); |
| 87 | print_debug_hex8(device); |
| 88 | |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 89 | if (device != DIMM0) { |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 90 | print_debug(" returns 0xff\n"); |
| 91 | return 0xff; |
| 92 | } |
| 93 | |
| 94 | print_debug(" addr "); |
| 95 | print_debug_hex8(address); |
| 96 | print_debug(" returns "); |
| 97 | print_debug_hex8(spdbytes[address]); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 98 | print_debug("\n"); |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 99 | |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 100 | return spdbytes[address]; |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 101 | } |
| 102 | |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 103 | #define ManualConf 0 /* Do automatic strapped PLL config */ |
| 104 | #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ |
| 105 | #define PLLMSRlo 0x02000030 |
| 106 | |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 107 | #include "northbridge/amd/lx/raminit.h" |
| 108 | #include "northbridge/amd/lx/pll_reset.c" |
| 109 | #include "northbridge/amd/lx/raminit.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 110 | #include "lib/generic_sdram.c" |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 111 | #include "cpu/amd/model_lx/cpureginit.c" |
| 112 | #include "cpu/amd/model_lx/syspreinit.c" |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 113 | #include "cpu/amd/model_lx/msrinit.c" |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 114 | |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 115 | void main(unsigned long bist) |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 116 | { |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 117 | static const struct mem_controller memctrl[] = { |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 118 | {.channel0 = {DIMM0}}, |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 119 | }; |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 120 | |
Stefan Reinauer | 0c781b2 | 2010-04-01 09:50:32 +0000 | [diff] [blame] | 121 | post_code(0x01); |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 122 | |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 123 | SystemPreInit(); |
| 124 | msr_init(); |
| 125 | |
| 126 | cs5536_early_setup(); |
| 127 | |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 128 | /* NOTE: Must do this AFTER cs5536_early_setup()! |
| 129 | * It is counting on some early MSR setup for the CS5536. |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 130 | */ |
| 131 | cs5536_disable_internal_uart(); |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 132 | w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 133 | uart_init(); |
| 134 | console_init(); |
| 135 | |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 136 | /* Halt if there was a built in self test failure */ |
| 137 | report_bist_failure(bist); |
| 138 | |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 139 | pll_reset(ManualConf); |
| 140 | |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 141 | cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 142 | |
| 143 | sdram_initialize(1, memctrl); |
| 144 | |
Ronald G. Minnich | cbc95f3 | 2007-09-09 19:43:31 +0000 | [diff] [blame] | 145 | /* Check memory */ |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 146 | /* Enable this only if you are having questions. */ |
| 147 | /* ram_check(0, 640 * 1024); */ |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 148 | |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 149 | /* Switch from Cache as RAM to real RAM. |
| 150 | * |
| 151 | * There are two ways we could think about this. |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 152 | * |
Stefan Reinauer | 38f147e | 2010-02-08 12:20:50 +0000 | [diff] [blame] | 153 | * 1. If we are using the romstage.inc ROMCC way, the stack is |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 154 | * going to be re-setup in the code following this code. Just |
| 155 | * wbinvd the stack to clear the cache tags. We don't care |
| 156 | * where the stack used to be. |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 157 | * |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 158 | * 2. This file is built as a normal .c -> .o and linked in |
| 159 | * etc. The stack might be used to return etc. That means we |
| 160 | * care about what is in the stack. If we are smart we set |
| 161 | * the CAR stack to the same location as the rest of |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 162 | * coreboot. If that is the case we can just do a wbinvd. |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 163 | * The stack will be written into real RAM that is now setup |
| 164 | * and we continue like nothing happened. If the stack is |
| 165 | * located somewhere other than where LB would like it, you |
| 166 | * need to write some code to do a copy from cache to RAM |
| 167 | * |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 168 | * We use method 1 on Norwich and on this board too. |
Ronald G. Minnich | 65bc460 | 2007-10-26 14:57:46 +0000 | [diff] [blame] | 169 | */ |
Stefan Reinauer | 0c781b2 | 2010-04-01 09:50:32 +0000 | [diff] [blame] | 170 | post_code(0x02); |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 171 | print_err("POST 02\n"); |
| 172 | __asm__("wbinvd\n"); |
| 173 | print_err("Past wbinvd\n"); |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 174 | |
| 175 | /* We are finding the return does not work on this board. Explicitly |
| 176 | * call the label that is after the call to us. This is gross, but |
| 177 | * sometimes at this level it is the only way out. |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 178 | */ |
Carl-Daniel Hailfinger | dbda3a9 | 2009-04-20 12:02:25 +0000 | [diff] [blame] | 179 | void done_cache_as_ram_main(void); |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 180 | done_cache_as_ram_main(); |
| 181 | } |