Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Ritul Guru | d3dae3d | 2022-04-04 13:33:01 +0530 | [diff] [blame] | 3 | config SOC_AMD_REMBRANDT_BASE |
| 4 | bool |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 5 | select ACPI_SOC_NVS |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 6 | select ARCH_X86 |
| 7 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 8 | select DRIVERS_USB_ACPI |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 9 | select DRIVERS_USB_PCI_XHCI |
| 10 | select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING |
| 11 | select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING |
| 12 | select FSP_COMPRESS_FSP_S_LZ4 |
| 13 | select GENERIC_GPIO_LIB |
| 14 | select HAVE_ACPI_TABLES |
| 15 | select HAVE_CF9_RESET |
| 16 | select HAVE_EM100_SUPPORT |
| 17 | select HAVE_FSP_GOP |
| 18 | select HAVE_SMI_HANDLER |
| 19 | select IDT_IN_EVERY_STAGE |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 20 | select NO_DDR4 |
| 21 | select NO_DDR3 |
| 22 | select NO_DDR2 |
| 23 | select NO_LPDDR4 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 24 | select PARALLEL_MP_AP_WORK |
| 25 | select PLATFORM_USES_FSP2_0 |
| 26 | select PROVIDES_ROM_SHARING |
Karthikeyan Ramasubramanian | 8ebb04c | 2022-07-14 17:29:06 -0600 | [diff] [blame] | 27 | select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Karthikeyan Ramasubramanian | b2af2e3 | 2022-08-04 14:16:38 -0600 | [diff] [blame] | 28 | select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 29 | select RESET_VECTOR_IN_RAM |
| 30 | select RTC |
| 31 | select SOC_AMD_COMMON |
Fred Reitberger | 81d3cde | 2022-02-10 09:31:26 -0500 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_ACP_GEN2 |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 33 | select SOC_AMD_COMMON_BLOCK_ACPI |
Felix Held | 70f32bb | 2022-02-04 16:23:47 +0100 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_ACPI_ALIB |
Felix Held | 665476d | 2022-08-03 22:18:18 +0200 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_ACPI_CPPC |
Felix Held | af803a6 | 2022-06-22 18:22:16 +0200 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_ACPI_IVRS |
Felix Held | 716ccb7 | 2022-02-03 18:27:29 +0100 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_AOAC |
Fred Reitberger | 8b570bd | 2022-09-06 12:19:38 -0400 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_APOB |
| 41 | select SOC_AMD_COMMON_BLOCK_APOB_HASH |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | 75739d3 | 2022-02-03 18:44:27 +0100 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Felix Held | 65d73cc | 2022-10-13 20:58:47 +0200 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_EMMC |
Felix Held | c64f37d | 2022-02-12 17:30:59 +0100 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Felix Held | c64f37d | 2022-02-12 17:30:59 +0100 | [diff] [blame] | 47 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Raul E Rangel | 5a5de33 | 2022-04-25 13:33:50 -0600 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE |
Felix Held | 8e4742d | 2022-02-03 15:15:37 +0100 | [diff] [blame] | 49 | select SOC_AMD_COMMON_BLOCK_I2C |
Felix Held | 3bdbdb7 | 2022-02-02 22:55:34 +0100 | [diff] [blame] | 50 | select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL |
Felix Held | 0eef54b | 2022-02-04 19:28:51 +0100 | [diff] [blame] | 51 | select SOC_AMD_COMMON_BLOCK_IOMMU |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 52 | select SOC_AMD_COMMON_BLOCK_LPC |
Karthikeyan Ramasubramanian | 5d5f682 | 2022-12-05 17:08:08 -0700 | [diff] [blame] | 53 | select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
Felix Held | 901481f | 2022-06-22 15:38:44 +0200 | [diff] [blame] | 54 | select SOC_AMD_COMMON_BLOCK_MCAX |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 55 | select SOC_AMD_COMMON_BLOCK_NONCAR |
| 56 | select SOC_AMD_COMMON_BLOCK_PCI |
Felix Held | ceefc74 | 2022-02-07 15:27:27 +0100 | [diff] [blame] | 57 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 58 | select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER |
Robert Zieba | b3b27f7 | 2022-10-03 14:50:55 -0600 | [diff] [blame] | 59 | select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 60 | select SOC_AMD_COMMON_BLOCK_PM |
| 61 | select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
| 62 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
| 63 | select SOC_AMD_COMMON_BLOCK_SMBUS |
| 64 | select SOC_AMD_COMMON_BLOCK_SMI |
| 65 | select SOC_AMD_COMMON_BLOCK_SMM |
Felix Held | 6f9e4ab | 2022-02-03 18:34:23 +0100 | [diff] [blame] | 66 | select SOC_AMD_COMMON_BLOCK_SMU |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 67 | select SOC_AMD_COMMON_BLOCK_SPI |
Martin Roth | 300338f | 2022-10-14 14:55:25 -0600 | [diff] [blame] | 68 | select SOC_AMD_COMMON_BLOCK_STB |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 69 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | b0789ed | 2022-02-04 22:36:32 +0100 | [diff] [blame] | 70 | select SOC_AMD_COMMON_BLOCK_UART |
Felix Held | d9bb9fc | 2022-06-22 15:35:35 +0200 | [diff] [blame] | 71 | select SOC_AMD_COMMON_BLOCK_UCODE |
Felix Held | 665476d | 2022-08-03 22:18:18 +0200 | [diff] [blame] | 72 | select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 73 | select SOC_AMD_COMMON_FSP_DMI_TABLES |
| 74 | select SOC_AMD_COMMON_FSP_PCI |
Fred Reitberger | 41c7e31 | 2023-01-11 15:11:08 -0500 | [diff] [blame] | 75 | select SOC_AMD_COMMON_FSP_PRELOAD_FSPS |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 76 | select SSE2 |
| 77 | select UDK_2017_BINDING |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 78 | select USE_DDR5 |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 79 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 80 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 81 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 82 | select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Karthikeyan Ramasubramanian | 06d5b8b | 2022-10-27 22:50:07 -0600 | [diff] [blame] | 83 | select VBOOT_X86_SHA256_ACCELERATION if VBOOT |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 84 | select X86_AMD_FIXED_MTRRS |
| 85 | select X86_INIT_NEED_1_SIPI |
| 86 | |
Elyes Haouas | 3cd06cc | 2023-01-05 07:42:24 +0100 | [diff] [blame] | 87 | config SOC_AMD_MENDOCINO |
| 88 | bool |
| 89 | select SOC_AMD_REMBRANDT_BASE |
| 90 | help |
| 91 | AMD Mendocino support |
| 92 | |
| 93 | config SOC_AMD_REMBRANDT |
| 94 | bool |
| 95 | select SOC_AMD_REMBRANDT_BASE |
| 96 | help |
| 97 | AMD Rembrandt support |
| 98 | |
| 99 | |
| 100 | if SOC_AMD_REMBRANDT_BASE |
| 101 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 102 | config CHIPSET_DEVICETREE |
| 103 | string |
Jon Murphy | 4f73242 | 2022-08-05 15:43:44 -0600 | [diff] [blame] | 104 | default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO |
| 105 | default "soc/amd/mendocino/chipset_rembrandt.cb" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 106 | |
| 107 | config EARLY_RESERVED_DRAM_BASE |
| 108 | hex |
| 109 | default 0x2000000 |
| 110 | help |
| 111 | This variable defines the base address of the DRAM which is reserved |
| 112 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 113 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 114 | not use it, thus preventing corruption of OS memory in case of S3 |
| 115 | resume. |
| 116 | |
| 117 | config EARLYRAM_BSP_STACK_SIZE |
| 118 | hex |
| 119 | default 0x1000 |
| 120 | |
| 121 | config PSP_APOB_DRAM_ADDRESS |
| 122 | hex |
| 123 | default 0x2001000 |
| 124 | help |
| 125 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 126 | Block. |
| 127 | |
Fred Reitberger | 475e282 | 2022-07-14 11:06:30 -0400 | [diff] [blame] | 128 | config PSP_APOB_DRAM_SIZE |
| 129 | hex |
Fred Reitberger | fdb0758 | 2022-07-15 08:05:56 -0400 | [diff] [blame] | 130 | default 0x1E000 |
Fred Reitberger | 475e282 | 2022-07-14 11:06:30 -0400 | [diff] [blame] | 131 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 132 | config PSP_SHAREDMEM_BASE |
| 133 | hex |
Fred Reitberger | fdb0758 | 2022-07-15 08:05:56 -0400 | [diff] [blame] | 134 | default 0x201F000 if VBOOT |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 135 | default 0x0 |
| 136 | help |
| 137 | This variable defines the base address in DRAM memory where PSP copies |
| 138 | the vboot workbuf. This is used in the linker script to have a static |
| 139 | allocation for the buffer as well as for adding relevant entries in |
| 140 | the BIOS directory table for the PSP. |
| 141 | |
| 142 | config PSP_SHAREDMEM_SIZE |
| 143 | hex |
| 144 | default 0x8000 if VBOOT |
| 145 | default 0x0 |
| 146 | help |
| 147 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 148 | any logs or timestamps back to coreboot. This will be copied |
| 149 | into main memory by the PSP and will be available when the x86 is |
| 150 | started. The workbuf's base depends on the address of the reset |
| 151 | vector. |
| 152 | |
Felix Held | 5561468 | 2022-01-25 04:31:15 +0100 | [diff] [blame] | 153 | config PRE_X86_CBMEM_CONSOLE_SIZE |
| 154 | hex |
Karthikeyan Ramasubramanian | 4763a5a4 | 2022-11-17 23:07:28 -0700 | [diff] [blame] | 155 | default 0x1000 |
Felix Held | 5561468 | 2022-01-25 04:31:15 +0100 | [diff] [blame] | 156 | help |
| 157 | Size of the CBMEM console used in PSP verstage. |
| 158 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 159 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 160 | hex |
| 161 | default 0x1600 |
| 162 | help |
| 163 | Increase this value if preram cbmem console is getting truncated |
| 164 | |
| 165 | config CBFS_MCACHE_SIZE |
| 166 | hex |
Karthikeyan Ramasubramanian | 4763a5a4 | 2022-11-17 23:07:28 -0700 | [diff] [blame] | 167 | default 0x3800 if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 168 | |
| 169 | config C_ENV_BOOTBLOCK_SIZE |
| 170 | hex |
| 171 | default 0x10000 |
| 172 | help |
| 173 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 174 | This variable controls the DRAM allocation size in linker script |
| 175 | for bootblock stage. |
| 176 | |
| 177 | config ROMSTAGE_ADDR |
| 178 | hex |
| 179 | default 0x2040000 |
| 180 | help |
| 181 | Sets the address in DRAM where romstage should be loaded. |
| 182 | |
| 183 | config ROMSTAGE_SIZE |
| 184 | hex |
| 185 | default 0x80000 |
| 186 | help |
| 187 | Sets the size of DRAM allocation for romstage in linker script. |
| 188 | |
| 189 | config FSP_M_ADDR |
| 190 | hex |
| 191 | default 0x20C0000 |
| 192 | help |
| 193 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 194 | performs relocation of FSP-M to this address. |
| 195 | |
| 196 | config FSP_M_SIZE |
| 197 | hex |
| 198 | default 0xC0000 |
| 199 | help |
| 200 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 201 | |
| 202 | config FSP_TEMP_RAM_SIZE |
| 203 | hex |
| 204 | default 0x40000 |
| 205 | help |
| 206 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 207 | |
| 208 | config VERSTAGE_ADDR |
| 209 | hex |
| 210 | depends on VBOOT_SEPARATE_VERSTAGE |
| 211 | default 0x2180000 |
| 212 | help |
| 213 | Sets the address in DRAM where verstage should be loaded if running |
| 214 | as a separate stage on x86. |
| 215 | |
| 216 | config VERSTAGE_SIZE |
| 217 | hex |
| 218 | depends on VBOOT_SEPARATE_VERSTAGE |
| 219 | default 0x80000 |
| 220 | help |
| 221 | Sets the size of DRAM allocation for verstage in linker script if |
| 222 | running as a separate stage on x86. |
| 223 | |
| 224 | config ASYNC_FILE_LOADING |
| 225 | bool "Loads files from SPI asynchronously" |
| 226 | select COOP_MULTITASKING |
| 227 | select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
| 228 | select CBFS_PRELOAD |
| 229 | help |
| 230 | When enabled, the platform will use the LPC SPI DMA controller to |
| 231 | asynchronously load contents from the SPI ROM. This will improve |
| 232 | boot time because the CPUs can be performing useful work while the |
| 233 | SPI contents are being preloaded. |
| 234 | |
| 235 | config CBFS_CACHE_SIZE |
| 236 | hex |
| 237 | default 0x40000 if CBFS_PRELOAD |
| 238 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 239 | config RO_REGION_ONLY |
| 240 | string |
| 241 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| 242 | default "apu/amdfw" |
| 243 | |
| 244 | config ECAM_MMCONF_BASE_ADDRESS |
| 245 | default 0xF8000000 |
| 246 | |
| 247 | config ECAM_MMCONF_BUS_NUMBER |
| 248 | default 64 |
| 249 | |
| 250 | config MAX_CPUS |
| 251 | int |
Jon Murphy | 4f73242 | 2022-08-05 15:43:44 -0600 | [diff] [blame] | 252 | default 8 if SOC_AMD_MENDOCINO |
Ritul Guru | d3dae3d | 2022-04-04 13:33:01 +0530 | [diff] [blame] | 253 | default 16 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 254 | help |
| 255 | Maximum number of threads the platform can have. |
| 256 | |
| 257 | config CONSOLE_UART_BASE_ADDRESS |
| 258 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 259 | hex |
| 260 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 261 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
Felix Held | b1fe9de | 2022-01-12 23:18:54 +0100 | [diff] [blame] | 262 | default 0xfedce000 if UART_FOR_CONSOLE = 2 |
| 263 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
| 264 | default 0xfedd1000 if UART_FOR_CONSOLE = 4 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 265 | |
| 266 | config SMM_TSEG_SIZE |
| 267 | hex |
| 268 | default 0x800000 if HAVE_SMI_HANDLER |
| 269 | default 0x0 |
| 270 | |
| 271 | config SMM_RESERVED_SIZE |
| 272 | hex |
| 273 | default 0x180000 |
| 274 | |
| 275 | config SMM_MODULE_STACK_SIZE |
| 276 | hex |
| 277 | default 0x800 |
| 278 | |
| 279 | config ACPI_BERT |
| 280 | bool "Build ACPI BERT Table" |
| 281 | default y |
| 282 | depends on HAVE_ACPI_TABLES |
| 283 | help |
| 284 | Report Machine Check errors identified in POST to the OS in an |
| 285 | ACPI Boot Error Record Table. |
| 286 | |
| 287 | config ACPI_BERT_SIZE |
| 288 | hex |
| 289 | default 0x4000 if ACPI_BERT |
| 290 | default 0x0 |
| 291 | help |
| 292 | Specify the amount of DRAM reserved for gathering the data used to |
| 293 | generate the ACPI table. |
| 294 | |
| 295 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 296 | int |
| 297 | default 150 |
| 298 | |
| 299 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 300 | def_bool n |
| 301 | help |
| 302 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 303 | which indicates a board level ROM transaction request. This |
| 304 | removes arbitration with board and assumes the chipset controls |
| 305 | the SPI flash bus entirely. |
| 306 | |
| 307 | config DISABLE_KEYBOARD_RESET_PIN |
| 308 | bool |
| 309 | help |
| 310 | Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| 311 | signal. When this pin is used as GPIO and the keyboard reset |
| 312 | functionality isn't disabled, configuring it as an output and driving |
| 313 | it as 0 will cause a reset. |
| 314 | |
| 315 | config ACPI_SSDT_PSD_INDEPENDENT |
| 316 | bool "Allow core p-state independent transitions" |
| 317 | default y |
| 318 | help |
| 319 | AMD recommends the ACPI _PSD object to be configured to cause |
| 320 | cores to transition between p-states independently. A vendor may |
| 321 | choose to generate _PSD object to allow cores to transition together. |
| 322 | |
Chris.Wang | 9ac0984 | 2022-12-13 14:31:38 +0800 | [diff] [blame] | 323 | config FEATURE_DYNAMIC_DPTC |
| 324 | bool |
| 325 | depends on SOC_AMD_COMMON_BLOCK_ACPI_DPTC |
| 326 | help |
| 327 | Selected by mainboards that implement support for ALIB |
| 328 | to enable dynamic DPTC. |
| 329 | |
| 330 | config FEATURE_TABLET_MODE_DPTC |
| 331 | bool |
| 332 | depends on SOC_AMD_COMMON_BLOCK_ACPI_DPTC |
| 333 | help |
| 334 | Selected by mainboards that implement support for ALIB to |
| 335 | switch default and tablet mode. |
| 336 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 337 | menu "PSP Configuration Options" |
| 338 | |
| 339 | config AMD_FWM_POSITION_INDEX |
| 340 | int "Firmware Directory Table location (0 to 5)" |
| 341 | range 0 5 |
| 342 | default 0 if BOARD_ROMSIZE_KB_512 |
| 343 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 344 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 345 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 346 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 347 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 348 | help |
| 349 | Typically this is calculated by the ROM size, but there may |
| 350 | be situations where you want to put the firmware directory |
| 351 | table in a different location. |
| 352 | 0: 512 KB - 0xFFFA0000 |
| 353 | 1: 1 MB - 0xFFF20000 |
| 354 | 2: 2 MB - 0xFFE20000 |
| 355 | 3: 4 MB - 0xFFC20000 |
| 356 | 4: 8 MB - 0xFF820000 |
| 357 | 5: 16 MB - 0xFF020000 |
| 358 | |
| 359 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 360 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 361 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 362 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 363 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 364 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 365 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 366 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 367 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 368 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 369 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 370 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 371 | |
| 372 | config AMDFW_CONFIG_FILE |
Karthikeyan Ramasubramanian | 9cb0a05 | 2022-03-21 17:49:11 -0600 | [diff] [blame] | 373 | string "AMD PSP Firmware config file" |
Jon Murphy | 4f73242 | 2022-08-05 15:43:44 -0600 | [diff] [blame] | 374 | default "src/soc/amd/mendocino/fw.cfg" |
Karthikeyan Ramasubramanian | 9cb0a05 | 2022-03-21 17:49:11 -0600 | [diff] [blame] | 375 | help |
| 376 | Specify the path/location of AMD PSP Firmware config file. |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 377 | |
| 378 | config PSP_DISABLE_POSTCODES |
| 379 | bool "Disable PSP post codes" |
| 380 | help |
| 381 | Disables the output of port80 post codes from PSP. |
| 382 | |
| 383 | config PSP_POSTCODES_ON_ESPI |
| 384 | bool "Use eSPI bus for PSP post codes" |
| 385 | default y |
| 386 | depends on !PSP_DISABLE_POSTCODES |
| 387 | help |
| 388 | Select to send PSP port80 post codes on eSPI bus. |
| 389 | If not selected, PSP port80 codes will be sent on LPC bus. |
| 390 | |
| 391 | config PSP_LOAD_MP2_FW |
| 392 | bool |
| 393 | default n |
| 394 | help |
| 395 | Include the MP2 firmwares and configuration into the PSP build. |
| 396 | |
| 397 | If unsure, answer 'n' |
| 398 | |
| 399 | config PSP_UNLOCK_SECURE_DEBUG |
| 400 | bool "Unlock secure debug" |
| 401 | default y |
| 402 | help |
| 403 | Select this item to enable secure debug options in PSP. |
| 404 | |
| 405 | config HAVE_PSP_WHITELIST_FILE |
| 406 | bool "Include a debug whitelist file in PSP build" |
| 407 | default n |
| 408 | help |
| 409 | Support secured unlock prior to reset using a whitelisted |
| 410 | serial number. This feature requires a signed whitelist image |
| 411 | and bootloader from AMD. |
| 412 | |
| 413 | If unsure, answer 'n' |
| 414 | |
| 415 | config PSP_WHITELIST_FILE |
| 416 | string "Debug whitelist file path" |
| 417 | depends on HAVE_PSP_WHITELIST_FILE |
Marshall Dawson | 84fef89 | 2022-08-05 12:13:49 -0600 | [diff] [blame] | 418 | default "site-local/3rdparty/amd_blobs/mendocino/PSP/wtl-mdn.sbin" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 419 | |
Karthikeyan Ramasubramanian | 8ee9429 | 2022-04-01 17:21:14 -0600 | [diff] [blame] | 420 | config HAVE_SPL_FILE |
| 421 | bool "Have a mainboard specific SPL table file" |
| 422 | default n |
| 423 | help |
| 424 | Have a mainboard specific Security Patch Level (SPL) table file. SPL file |
| 425 | is required to support PSP FW anti-rollback and needs to be created by AMD. |
| 426 | The default SPL file applies to all boards that use the concerned SoC and |
| 427 | is dropped under 3rdparty/blobs. The mainboard specific SPL file override |
| 428 | can be applied through SPL_TABLE_FILE config. |
| 429 | |
| 430 | If unsure, answer 'n' |
| 431 | |
| 432 | config SPL_TABLE_FILE |
| 433 | string "SPL table file" |
| 434 | depends on HAVE_SPL_FILE |
Marshall Dawson | 26d7d73 | 2022-08-05 12:44:03 -0600 | [diff] [blame] | 435 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin" |
Karthikeyan Ramasubramanian | 8ee9429 | 2022-04-01 17:21:14 -0600 | [diff] [blame] | 436 | |
Felix Held | 40a38cc | 2022-09-12 16:18:45 +0200 | [diff] [blame] | 437 | config HAVE_SPL_RW_AB_FILE |
| 438 | bool "Have a separate mainboard-specific SPL file in RW A/B partitions" |
| 439 | default n |
| 440 | depends on HAVE_SPL_FILE |
| 441 | depends on VBOOT_SLOTS_RW_AB |
| 442 | help |
| 443 | Have separate mainboard-specific Security Patch Level (SPL) table |
| 444 | file for the RW A/B FMAP partitions. See the help text of |
| 445 | HAVE_SPL_FILE for a more detailed description. |
| 446 | |
| 447 | config SPL_RW_AB_TABLE_FILE |
| 448 | string "Separate SPL table file for RW A/B partitions" |
| 449 | depends on HAVE_SPL_RW_AB_FILE |
| 450 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin" |
| 451 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 452 | config PSP_SOFTFUSE_BITS |
| 453 | string "PSP Soft Fuse bits to enable" |
Felix Held | ed69450 | 2022-06-22 15:09:23 +0200 | [diff] [blame] | 454 | default "34 28 6" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 455 | help |
| 456 | Space separated list of Soft Fuse bits to enable. |
| 457 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 458 | Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| 459 | (Set by PSP_DISABLE_PORT80) |
Felix Held | c357900 | 2022-03-23 22:15:56 +0100 | [diff] [blame] | 460 | Bit 15: PSP debug output destination: |
| 461 | 0=SoC MMIO UART, 1=IO port 0x3F8 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 462 | Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| 463 | |
| 464 | See #55758 (NDA) for additional bit definitions. |
| 465 | |
| 466 | config PSP_VERSTAGE_FILE |
| 467 | string "Specify the PSP_verstage file path" |
| 468 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 469 | default "\$(obj)/psp_verstage.bin" |
| 470 | help |
| 471 | Add psp_verstage file to the build & PSP Directory Table |
| 472 | |
| 473 | config PSP_VERSTAGE_SIGNING_TOKEN |
| 474 | string "Specify the PSP_verstage Signature Token file path" |
| 475 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 476 | default "" |
| 477 | help |
| 478 | Add psp_verstage signature token to the build & PSP Directory Table |
| 479 | |
| 480 | endmenu |
| 481 | |
| 482 | config VBOOT |
| 483 | select VBOOT_VBNV_CMOS |
| 484 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 485 | |
| 486 | config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 487 | def_bool n |
| 488 | depends on VBOOT |
| 489 | select ARCH_VERSTAGE_ARMV7 |
| 490 | help |
| 491 | Runs verstage on the PSP. Only available on |
Jon Murphy | c4e9045 | 2022-06-28 10:36:23 -0600 | [diff] [blame] | 492 | certain ChromeOS branded parts from AMD. |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 493 | |
| 494 | config VBOOT_HASH_BLOCK_SIZE |
| 495 | hex |
| 496 | default 0x9000 |
| 497 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 498 | help |
| 499 | Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| 500 | spent in the overhead of doing svc calls, increasing the hash block |
| 501 | size significantly cuts the verstage hashing time as seen below. |
| 502 | |
| 503 | 4k takes 180ms |
| 504 | 16k takes 44ms |
| 505 | 32k takes 33.7ms |
| 506 | 36k takes 32.5ms |
| 507 | There's actually still room for an even bigger stack, but we've |
| 508 | reached a point of diminishing returns. |
| 509 | |
| 510 | config CMOS_RECOVERY_BYTE |
| 511 | hex |
| 512 | default 0x51 |
| 513 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 514 | help |
| 515 | If the workbuf is not passed from the PSP to coreboot, set the |
| 516 | recovery flag and reboot. The PSP will read this byte, mark the |
| 517 | recovery request in VBNV, and reset the system into recovery mode. |
| 518 | |
| 519 | This is the byte before the default first byte used by VBNV |
| 520 | (0x26 + 0x0E - 1) |
| 521 | |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 522 | if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 523 | |
| 524 | config RWA_REGION_ONLY |
| 525 | string |
Karthikeyan Ramasubramanian | 716c8f0 | 2022-12-15 14:57:05 -0700 | [diff] [blame] | 526 | default "apu/amdfw_a apu/amdfw_a_body" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 527 | help |
| 528 | Add a space-delimited list of filenames that should only be in the |
| 529 | RW-A section. |
| 530 | |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 531 | endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 532 | |
| 533 | if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 534 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 535 | config RWB_REGION_ONLY |
| 536 | string |
Karthikeyan Ramasubramanian | 716c8f0 | 2022-12-15 14:57:05 -0700 | [diff] [blame] | 537 | default "apu/amdfw_b apu/amdfw_b_body" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 538 | help |
| 539 | Add a space-delimited list of filenames that should only be in the |
| 540 | RW-B section. |
| 541 | |
| 542 | endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 543 | |
Ritul Guru | d3dae3d | 2022-04-04 13:33:01 +0530 | [diff] [blame] | 544 | endif # SOC_AMD_REMBRANDT_BASE |