Angel Pons | 1ddb894 | 2020-04-04 18:51:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 2 | |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 3 | #include <arch/cache.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <ec/google/chromeec/ec.h> |
| 8 | #include <soc/dp.h> |
| 9 | #include <soc/fimd.h> |
| 10 | #include <soc/cpu.h> |
| 11 | #include <soc/clk.h> |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 12 | #include <string.h> |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 13 | |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 14 | #include "chip.h" |
David Hendricks | c81187f | 2013-08-01 19:09:21 -0700 | [diff] [blame] | 15 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 16 | static unsigned int cpu_id; |
| 17 | static unsigned int cpu_rev; |
| 18 | |
| 19 | static void set_cpu_id(void) |
| 20 | { |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 21 | u32 pro_id = (read32((void *)EXYNOS5_PRO_ID) & 0x00FFF000) >> 12; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 22 | |
David Hendricks | d598cac | 2013-08-01 18:17:55 -0700 | [diff] [blame] | 23 | switch (pro_id) { |
| 24 | case 0x200: |
| 25 | /* Exynos4210 EVT0 */ |
| 26 | cpu_id = 0x4210; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 27 | cpu_rev = 0; |
David Hendricks | d598cac | 2013-08-01 18:17:55 -0700 | [diff] [blame] | 28 | break; |
| 29 | case 0x210: |
| 30 | /* Exynos4210 EVT1 */ |
| 31 | cpu_id = 0x4210; |
| 32 | break; |
| 33 | case 0x412: |
| 34 | /* Exynos4412 */ |
| 35 | cpu_id = 0x4412; |
| 36 | break; |
| 37 | case 0x520: |
| 38 | /* Exynos5250 */ |
| 39 | cpu_id = 0x5250; |
| 40 | break; |
| 41 | case 0x420: |
| 42 | /* Exynos5420 */ |
| 43 | cpu_id = 0x5420; |
| 44 | break; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 45 | } |
| 46 | } |
| 47 | |
| 48 | /* we distinguish a display port device from a raw graphics device |
| 49 | * because there are dramatic differences in startup depending on |
| 50 | * graphics usage. To make startup fast and easier to understand and |
| 51 | * debug we explicitly name this common case. The alternate approach, |
| 52 | * involving lots of machine and callbacks, is hard to debug and |
| 53 | * verify. |
| 54 | */ |
Elyes HAOUAS | 0111533 | 2018-05-25 09:15:21 +0200 | [diff] [blame] | 55 | static void exynos_displayport_init(struct device *dev, u32 lcdbase, |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 56 | unsigned long fb_size) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 57 | { |
Hung-Te Lin | 22d0ca0 | 2013-09-27 12:45:45 +0800 | [diff] [blame] | 58 | struct soc_samsung_exynos5420_config *conf = dev->chip_info; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 59 | /* put these on the stack. If, at some point, we want to move |
| 60 | * this code to a pre-ram stage, it will be much easier. |
| 61 | */ |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 62 | struct exynos5_fimd_panel panel; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 63 | memset(&panel, 0, sizeof(panel)); |
| 64 | |
| 65 | panel.is_dp = 1; /* Display I/F is eDP */ |
| 66 | /* while it is true that we did a memset to zero, |
| 67 | * we leave some 'set to zero' entries here to make |
| 68 | * it clear what's going on. Graphics is confusing. |
| 69 | */ |
| 70 | panel.is_mipi = 0; |
| 71 | panel.fixvclk = 0; |
| 72 | panel.ivclk = 0; |
| 73 | panel.clkval_f = conf->clkval_f; |
| 74 | panel.upper_margin = conf->upper_margin; |
| 75 | panel.lower_margin = conf->lower_margin; |
| 76 | panel.vsync = conf->vsync; |
| 77 | panel.left_margin = conf->left_margin; |
| 78 | panel.right_margin = conf->right_margin; |
| 79 | panel.hsync = conf->hsync; |
| 80 | panel.xres = conf->xres; |
| 81 | panel.yres = conf->yres; |
| 82 | |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 83 | printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); |
Stefan Reinauer | 2d81125 | 2013-05-20 15:24:13 -0700 | [diff] [blame] | 84 | memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ |
| 85 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 86 | /* |
| 87 | * We need to clean and invalidate the framebuffer region and disable |
| 88 | * caching as well. We assume that our dcache <--> memory address |
| 89 | * space is identity-mapped in 1MB chunks, so align accordingly. |
| 90 | * |
| 91 | * Note: We may want to do something clever to ensure the framebuffer |
| 92 | * region is aligned such that we don't change dcache policy for other |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 93 | * stuff inadvertently. |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 94 | */ |
| 95 | uint32_t lower = ALIGN_DOWN(lcdbase, MiB); |
Stefan Reinauer | f175191 | 2013-05-20 15:17:44 -0700 | [diff] [blame] | 96 | uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 97 | |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 98 | dcache_clean_invalidate_by_mva((void *)lower, upper - lower); |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 99 | mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 100 | } |
| 101 | |
David Hendricks | c81187f | 2013-08-01 19:09:21 -0700 | [diff] [blame] | 102 | static void tps65090_thru_ec_fet_disable(int index) |
| 103 | { |
| 104 | uint8_t value = 0; |
| 105 | |
| 106 | if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { |
| 107 | printk(BIOS_ERR, |
| 108 | "Error sending i2c pass through command to EC.\n"); |
| 109 | return; |
| 110 | } |
| 111 | } |
| 112 | |
Elyes HAOUAS | 0111533 | 2018-05-25 09:15:21 +0200 | [diff] [blame] | 113 | static void cpu_enable(struct device *dev) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 114 | { |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 115 | unsigned long fb_size = FB_SIZE_KB * KiB; |
| 116 | u32 lcdbase = get_fb_base_kb() * KiB; |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 117 | |
David Hendricks | c81187f | 2013-08-01 19:09:21 -0700 | [diff] [blame] | 118 | /* |
| 119 | * Disable LCD FETs before we do anything with the display. |
| 120 | * FIXME(dhendrix): This is a gross hack and should be done |
| 121 | * elsewhere (romstage?). |
| 122 | */ |
| 123 | tps65090_thru_ec_fet_disable(1); |
| 124 | tps65090_thru_ec_fet_disable(6); |
| 125 | |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 126 | exynos_displayport_init(dev, lcdbase, fb_size); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 127 | |
| 128 | set_cpu_id(); |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 129 | } |
| 130 | |
Furquan Shaikh | cd6804c | 2020-05-13 12:22:53 -0700 | [diff] [blame] | 131 | static void cpu_read_resources(struct device *dev) |
| 132 | { |
| 133 | unsigned long fb_size = FB_SIZE_KB * KiB; |
| 134 | u32 lcdbase = get_fb_base_kb() * KiB; |
| 135 | |
Kyösti Mälkki | c9a0301 | 2021-06-26 14:14:56 +0300 | [diff] [blame] | 136 | ram_range(dev, 0, RAM_BASE_KB * KiB, (RAM_SIZE_KB - FB_SIZE_KB) * KiB); |
| 137 | mmio_range(dev, 1, lcdbase, fb_size); |
Furquan Shaikh | cd6804c | 2020-05-13 12:22:53 -0700 | [diff] [blame] | 138 | } |
| 139 | |
Elyes HAOUAS | 0111533 | 2018-05-25 09:15:21 +0200 | [diff] [blame] | 140 | static void cpu_init(struct device *dev) |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 141 | { |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 142 | printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", |
David Hendricks | 56a7cff | 2013-08-05 18:53:15 -0700 | [diff] [blame] | 143 | cpu_id, get_arm_clk() / 1000000); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 146 | static struct device_operations cpu_ops = { |
Furquan Shaikh | cd6804c | 2020-05-13 12:22:53 -0700 | [diff] [blame] | 147 | .read_resources = cpu_read_resources, |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 148 | .set_resources = noop_set_resources, |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 149 | .enable_resources = cpu_enable, |
| 150 | .init = cpu_init, |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 151 | }; |
| 152 | |
Elyes HAOUAS | 0111533 | 2018-05-25 09:15:21 +0200 | [diff] [blame] | 153 | static void enable_exynos5420_dev(struct device *dev) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 154 | { |
| 155 | dev->ops = &cpu_ops; |
| 156 | } |
| 157 | |
Gabe Black | d81f409 | 2013-10-08 23:16:51 -0700 | [diff] [blame] | 158 | struct chip_operations soc_samsung_exynos5420_ops = { |
| 159 | CHIP_NAME("SOC Samsung Exynos 5420") |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 160 | .enable_dev = enable_exynos5420_dev, |
| 161 | }; |