Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
Ronald G. Minnich | b0efbd3 | 2013-08-05 15:56:37 -0700 | [diff] [blame] | 5 | * Copyright (C) 2012 Samsung Electronics |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdlib.h> |
| 22 | #include <string.h> |
| 23 | #include <stddef.h> |
| 24 | #include <delay.h> |
| 25 | #include <console/console.h> |
| 26 | #include <device/device.h> |
| 27 | #include <cbmem.h> |
| 28 | #include <arch/cache.h> |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 29 | #include "dp.h" |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 30 | #include "fimd.h" |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 31 | #include "cpu.h" |
| 32 | #include "clk.h" |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 33 | #include "usb.h" |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 34 | #include "chip.h" |
| 35 | |
David Hendricks | c81187f | 2013-08-01 19:09:21 -0700 | [diff] [blame^] | 36 | #include <ec/google/chromeec/ec.h> |
| 37 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 38 | static unsigned int cpu_id; |
| 39 | static unsigned int cpu_rev; |
| 40 | |
Ronald G. Minnich | b0efbd3 | 2013-08-05 15:56:37 -0700 | [diff] [blame] | 41 | /* Setting TZPC[TrustZone Protection Controller] |
| 42 | * We pretty much disable it all, as the kernel |
| 43 | * expects it that way -- and that's not the default. |
| 44 | */ |
| 45 | static void tzpc_init(void) |
| 46 | { |
| 47 | struct exynos_tzpc *tzpc; |
| 48 | unsigned int addr; |
| 49 | |
| 50 | for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { |
| 51 | tzpc = (struct exynos_tzpc *)addr; |
| 52 | if (addr == TZPC0_BASE) |
| 53 | writel(R0SIZE, &tzpc->r0size); |
| 54 | writel(DECPROTXSET, &tzpc->decprot0set); |
| 55 | writel(DECPROTXSET, &tzpc->decprot1set); |
| 56 | writel(DECPROTXSET, &tzpc->decprot2set); |
| 57 | writel(DECPROTXSET, &tzpc->decprot3set); |
| 58 | } |
| 59 | } |
| 60 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 61 | static void set_cpu_id(void) |
| 62 | { |
David Hendricks | d598cac | 2013-08-01 18:17:55 -0700 | [diff] [blame] | 63 | u32 pro_id = (read32((void *)EXYNOS_PRO_ID) & 0x00FFF000) >> 12; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 64 | |
David Hendricks | d598cac | 2013-08-01 18:17:55 -0700 | [diff] [blame] | 65 | switch (pro_id) { |
| 66 | case 0x200: |
| 67 | /* Exynos4210 EVT0 */ |
| 68 | cpu_id = 0x4210; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 69 | cpu_rev = 0; |
David Hendricks | d598cac | 2013-08-01 18:17:55 -0700 | [diff] [blame] | 70 | break; |
| 71 | case 0x210: |
| 72 | /* Exynos4210 EVT1 */ |
| 73 | cpu_id = 0x4210; |
| 74 | break; |
| 75 | case 0x412: |
| 76 | /* Exynos4412 */ |
| 77 | cpu_id = 0x4412; |
| 78 | break; |
| 79 | case 0x520: |
| 80 | /* Exynos5250 */ |
| 81 | cpu_id = 0x5250; |
| 82 | break; |
| 83 | case 0x420: |
| 84 | /* Exynos5420 */ |
| 85 | cpu_id = 0x5420; |
| 86 | break; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 87 | } |
| 88 | } |
| 89 | |
| 90 | /* we distinguish a display port device from a raw graphics device |
| 91 | * because there are dramatic differences in startup depending on |
| 92 | * graphics usage. To make startup fast and easier to understand and |
| 93 | * debug we explicitly name this common case. The alternate approach, |
| 94 | * involving lots of machine and callbacks, is hard to debug and |
| 95 | * verify. |
| 96 | */ |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 97 | static void exynos_displayport_init(device_t dev, u32 lcdbase, |
| 98 | unsigned long fb_size) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 99 | { |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 100 | struct cpu_samsung_exynos5420_config *conf = dev->chip_info; |
| 101 | /* put these on the stack. If, at some point, we want to move |
| 102 | * this code to a pre-ram stage, it will be much easier. |
| 103 | */ |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 104 | struct exynos5_fimd_panel panel; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 105 | memset(&panel, 0, sizeof(panel)); |
| 106 | |
| 107 | panel.is_dp = 1; /* Display I/F is eDP */ |
| 108 | /* while it is true that we did a memset to zero, |
| 109 | * we leave some 'set to zero' entries here to make |
| 110 | * it clear what's going on. Graphics is confusing. |
| 111 | */ |
| 112 | panel.is_mipi = 0; |
| 113 | panel.fixvclk = 0; |
| 114 | panel.ivclk = 0; |
| 115 | panel.clkval_f = conf->clkval_f; |
| 116 | panel.upper_margin = conf->upper_margin; |
| 117 | panel.lower_margin = conf->lower_margin; |
| 118 | panel.vsync = conf->vsync; |
| 119 | panel.left_margin = conf->left_margin; |
| 120 | panel.right_margin = conf->right_margin; |
| 121 | panel.hsync = conf->hsync; |
| 122 | panel.xres = conf->xres; |
| 123 | panel.yres = conf->yres; |
| 124 | |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 125 | printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); |
Stefan Reinauer | 2d81125 | 2013-05-20 15:24:13 -0700 | [diff] [blame] | 126 | memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ |
| 127 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 128 | /* |
| 129 | * We need to clean and invalidate the framebuffer region and disable |
| 130 | * caching as well. We assume that our dcache <--> memory address |
| 131 | * space is identity-mapped in 1MB chunks, so align accordingly. |
| 132 | * |
| 133 | * Note: We may want to do something clever to ensure the framebuffer |
| 134 | * region is aligned such that we don't change dcache policy for other |
| 135 | * stuff inadvertantly. |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 136 | */ |
| 137 | uint32_t lower = ALIGN_DOWN(lcdbase, MiB); |
Stefan Reinauer | f175191 | 2013-05-20 15:17:44 -0700 | [diff] [blame] | 138 | uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 139 | |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 140 | dcache_clean_invalidate_by_mva(lower, upper - lower); |
| 141 | mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); |
| 142 | |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 143 | mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 144 | } |
| 145 | |
David Hendricks | c81187f | 2013-08-01 19:09:21 -0700 | [diff] [blame^] | 146 | static void tps65090_thru_ec_fet_disable(int index) |
| 147 | { |
| 148 | uint8_t value = 0; |
| 149 | |
| 150 | if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { |
| 151 | printk(BIOS_ERR, |
| 152 | "Error sending i2c pass through command to EC.\n"); |
| 153 | return; |
| 154 | } |
| 155 | } |
| 156 | |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 157 | static void cpu_enable(device_t dev) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 158 | { |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 159 | unsigned long fb_size = FB_SIZE_KB * KiB; |
| 160 | u32 lcdbase = get_fb_base_kb() * KiB; |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 161 | |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 162 | ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); |
| 163 | mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); |
| 164 | |
David Hendricks | c81187f | 2013-08-01 19:09:21 -0700 | [diff] [blame^] | 165 | /* |
| 166 | * Disable LCD FETs before we do anything with the display. |
| 167 | * FIXME(dhendrix): This is a gross hack and should be done |
| 168 | * elsewhere (romstage?). |
| 169 | */ |
| 170 | tps65090_thru_ec_fet_disable(1); |
| 171 | tps65090_thru_ec_fet_disable(6); |
| 172 | |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 173 | exynos_displayport_init(dev, lcdbase, fb_size); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 174 | |
| 175 | set_cpu_id(); |
Ronald G. Minnich | b0efbd3 | 2013-08-05 15:56:37 -0700 | [diff] [blame] | 176 | |
| 177 | tzpc_init(); |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static void cpu_init(device_t dev) |
| 181 | { |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 182 | printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", |
David Hendricks | 56a7cff | 2013-08-05 18:53:15 -0700 | [diff] [blame] | 183 | cpu_id, get_arm_clk() / 1000000); |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 184 | |
| 185 | usb_init(dev); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | static void cpu_noop(device_t dev) |
| 189 | { |
| 190 | } |
| 191 | |
| 192 | static struct device_operations cpu_ops = { |
| 193 | .read_resources = cpu_noop, |
| 194 | .set_resources = cpu_noop, |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 195 | .enable_resources = cpu_enable, |
| 196 | .init = cpu_init, |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 197 | .scan_bus = 0, |
| 198 | }; |
| 199 | |
| 200 | static void enable_exynos5420_dev(device_t dev) |
| 201 | { |
| 202 | dev->ops = &cpu_ops; |
| 203 | } |
| 204 | |
| 205 | struct chip_operations cpu_samsung_exynos5420_ops = { |
| 206 | CHIP_NAME("CPU Samsung Exynos 5420") |
| 207 | .enable_dev = enable_exynos5420_dev, |
| 208 | }; |
| 209 | |
| 210 | void exynos5420_config_l2_cache(void) |
| 211 | { |
| 212 | uint32_t val; |
| 213 | |
| 214 | /* |
| 215 | * Bit 9 - L2 tag RAM setup (1 cycle) |
| 216 | * Bits 8:6 - L2 tag RAM latency (3 cycles) |
| 217 | * Bit 5 - L2 data RAM setup (1 cycle) |
| 218 | * Bits 2:0 - L2 data RAM latency (3 cycles) |
| 219 | */ |
| 220 | val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); |
| 221 | write_l2ctlr(val); |
David Hendricks | 49c1be9 | 2013-08-06 18:05:55 -0700 | [diff] [blame] | 222 | |
| 223 | val = read_l2actlr(); |
| 224 | |
| 225 | /* L2ACTLR[3]: Disable clean/evict push to external */ |
| 226 | val |= (1 << 3); |
| 227 | |
| 228 | /* L2ACTLR[7]: Enable hazard detect timeout for A15 */ |
| 229 | val |= (1 << 7); |
| 230 | |
| 231 | /* L2ACTLR[27]: Prevents stopping the L2 logic clock */ |
| 232 | val |= (1 << 27); |
| 233 | |
| 234 | write_l2actlr(val); |
| 235 | |
| 236 | /* Read the l2 control register to force things to take effect? */ |
| 237 | val = read_l2ctlr(); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 238 | } |