Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 4 | #include <soc/addressmap.h> |
| 5 | #include <soc/grf.h> |
| 6 | #include <soc/soc.h> |
| 7 | #include <soc/pwm.h> |
| 8 | #include <soc/clock.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 9 | #include <timer.h> |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 10 | |
| 11 | struct pwm_ctl { |
| 12 | u32 pwm_cnt; |
| 13 | u32 pwm_period_hpr; |
| 14 | u32 pwm_duty_lpr; |
| 15 | u32 pwm_ctrl; |
| 16 | }; |
| 17 | |
Lin Huang | 6d6b129 | 2016-03-23 19:35:46 +0800 | [diff] [blame] | 18 | struct rk_pwm_regs { |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 19 | struct pwm_ctl pwm[4]; |
| 20 | u32 intsts; |
| 21 | u32 int_en; |
| 22 | }; |
Lin Huang | 6d6b129 | 2016-03-23 19:35:46 +0800 | [diff] [blame] | 23 | check_member(rk_pwm_regs, int_en, 0x44); |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 24 | |
| 25 | #define RK_PWM_DISABLE (0 << 0) |
| 26 | #define RK_PWM_ENABLE (1 << 0) |
| 27 | |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 28 | #define PWM_ONE_SHOT (0 << 1) |
| 29 | #define PWM_CONTINUOUS (1 << 1) |
| 30 | #define RK_PWM_CAPTURE (1 << 2) |
| 31 | |
| 32 | #define PWM_DUTY_POSTIVE (1 << 3) |
| 33 | #define PWM_DUTY_NEGATIVE (0 << 3) |
| 34 | |
| 35 | #define PWM_INACTIVE_POSTIVE (1 << 4) |
| 36 | #define PWM_INACTIVE_NEGATIVE (0 << 4) |
| 37 | |
| 38 | #define PWM_OUTPUT_LEFT (0 << 5) |
| 39 | #define PWM_OUTPUT_CENTER (1 << 5) |
| 40 | |
| 41 | #define PWM_LP_ENABLE (1 << 8) |
| 42 | #define PWM_LP_DISABLE (0 << 8) |
| 43 | |
| 44 | #define PWM_SEL_SCALE_CLK (1 << 9) |
| 45 | #define PWM_SEL_SRC_CLK (0 << 9) |
| 46 | |
Lin Huang | 6d6b129 | 2016-03-23 19:35:46 +0800 | [diff] [blame] | 47 | struct rk_pwm_regs *rk_pwm = (void *)RK_PWM_BASE; |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 48 | |
| 49 | void pwm_init(u32 id, u32 period_ns, u32 duty_ns) |
| 50 | { |
| 51 | unsigned long period, duty; |
| 52 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 53 | #if CONFIG(SOC_ROCKCHIP_RK3288) |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 54 | /*use rk pwm*/ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 55 | write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0)); |
Lin Huang | 6d6b129 | 2016-03-23 19:35:46 +0800 | [diff] [blame] | 56 | #endif |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 57 | |
Lin Huang | 6d6b129 | 2016-03-23 19:35:46 +0800 | [diff] [blame] | 58 | write32(&rk_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK | |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 59 | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS | |
| 60 | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE); |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 61 | |
Lin Huang | 6d6b129 | 2016-03-23 19:35:46 +0800 | [diff] [blame] | 62 | period = (PWM_CLOCK_HZ / 1000) * period_ns / USECS_PER_SEC; |
| 63 | duty = (PWM_CLOCK_HZ / 1000) * duty_ns / USECS_PER_SEC; |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 64 | |
Lin Huang | 6d6b129 | 2016-03-23 19:35:46 +0800 | [diff] [blame] | 65 | write32(&rk_pwm->pwm[id].pwm_period_hpr, period); |
| 66 | write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 67 | setbits32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 68 | } |