Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 2 | |
| 3 | #include <cbmem.h> |
| 4 | #include <romstage_handoff.h> |
| 5 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 7 | #include <arch/romstage.h> |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 8 | #include <northbridge/intel/gm45/gm45.h> |
| 9 | #include <southbridge/intel/i82801ix/i82801ix.h> |
| 10 | #include <southbridge/intel/common/gpio.h> |
Patrick Rudolph | ad0b482 | 2019-04-13 16:56:23 +0200 | [diff] [blame] | 11 | #include <southbridge/intel/common/pmclib.h> |
Angel Pons | e1a616c | 2020-06-21 17:02:43 +0200 | [diff] [blame] | 12 | #include <southbridge/intel/common/pmutil.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 13 | #include <string.h> |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 14 | |
| 15 | #define LPC_DEV PCI_DEV(0, 0x1f, 0) |
| 16 | #define MCH_DEV PCI_DEV(0, 0, 0) |
| 17 | |
| 18 | void __weak mb_setup_superio(void) |
| 19 | { |
| 20 | } |
| 21 | |
| 22 | void __weak mb_pre_raminit_setup(sysinfo_t *sysinfo) |
| 23 | { |
| 24 | } |
| 25 | |
| 26 | void __weak mb_post_raminit_setup(void) |
| 27 | { |
| 28 | } |
| 29 | |
| 30 | /* Platform has no romstage entry point under mainboard directory, |
| 31 | * so this one is named with prefix mainboard. |
| 32 | */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 33 | void mainboard_romstage_entry(void) |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 34 | { |
| 35 | sysinfo_t sysinfo; |
| 36 | int s3resume = 0; |
| 37 | int cbmem_initted; |
| 38 | u16 reg16; |
| 39 | |
| 40 | /* basic northbridge setup, including MMCONF BAR */ |
| 41 | gm45_early_init(); |
| 42 | |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 43 | /* First, run everything needed for console output. */ |
| 44 | i82801ix_early_init(); |
| 45 | setup_pch_gpios(&mainboard_gpio_map); |
| 46 | |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 47 | reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); |
| 48 | pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 49 | if ((mchbar_read16(SSKPD_MCHBAR) == 0xcafe) && !(reg16 & (1 << 9))) { |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 50 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 51 | gm45_early_reset(); |
| 52 | } |
| 53 | |
| 54 | /* ASPM related setting, set early by original BIOS. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 55 | dmibar_clrbits16(0x204, 3 << 10); |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 56 | |
| 57 | /* Check for S3 resume. */ |
Patrick Rudolph | ad0b482 | 2019-04-13 16:56:23 +0200 | [diff] [blame] | 58 | s3resume = southbridge_detect_s3_resume(); |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 59 | |
| 60 | /* RAM initialization */ |
| 61 | enter_raminit_or_reset(); |
| 62 | memset(&sysinfo, 0, sizeof(sysinfo)); |
| 63 | get_mb_spd_addrmap(sysinfo.spd_map); |
| 64 | const struct device *dev; |
| 65 | dev = pcidev_on_root(2, 0); |
| 66 | if (dev) |
| 67 | sysinfo.enable_igd = dev->enabled; |
| 68 | dev = pcidev_on_root(1, 0); |
| 69 | if (dev) |
| 70 | sysinfo.enable_peg = dev->enabled; |
| 71 | get_gmch_info(&sysinfo); |
| 72 | |
| 73 | mb_pre_raminit_setup(&sysinfo); |
| 74 | |
| 75 | raminit(&sysinfo, s3resume); |
| 76 | |
| 77 | mb_post_raminit_setup(); |
| 78 | |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 79 | /* Disable D4F0 (unknown signal controller). */ |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 80 | pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000); |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 81 | |
| 82 | init_pm(&sysinfo, 0); |
| 83 | |
| 84 | i82801ix_dmi_setup(); |
| 85 | gm45_late_init(sysinfo.stepping); |
| 86 | i82801ix_dmi_poll_vc1(); |
| 87 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 88 | mchbar_write16(SSKPD_MCHBAR, 0xcafe); |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 89 | |
| 90 | init_iommu(); |
| 91 | |
| 92 | cbmem_initted = !cbmem_recovery(s3resume); |
| 93 | |
| 94 | romstage_handoff_init(cbmem_initted && s3resume); |
| 95 | |
| 96 | printk(BIOS_SPEW, "exit main()\n"); |
| 97 | } |