Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <cbmem.h> |
| 19 | #include <romstage_handoff.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 23 | #include <arch/acpi.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <cpu/x86/bist.h> |
| 26 | #include <cpu/intel/romstage.h> |
| 27 | #include <northbridge/intel/gm45/gm45.h> |
| 28 | #include <southbridge/intel/i82801ix/i82801ix.h> |
| 29 | #include <southbridge/intel/common/gpio.h> |
Patrick Rudolph | ad0b482 | 2019-04-13 16:56:23 +0200 | [diff] [blame^] | 30 | #include <southbridge/intel/common/pmclib.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 31 | #include <string.h> |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 32 | |
| 33 | #define LPC_DEV PCI_DEV(0, 0x1f, 0) |
| 34 | #define MCH_DEV PCI_DEV(0, 0, 0) |
| 35 | |
| 36 | void __weak mb_setup_superio(void) |
| 37 | { |
| 38 | } |
| 39 | |
| 40 | void __weak mb_pre_raminit_setup(sysinfo_t *sysinfo) |
| 41 | { |
| 42 | } |
| 43 | |
| 44 | void __weak mb_post_raminit_setup(void) |
| 45 | { |
| 46 | } |
| 47 | |
| 48 | /* Platform has no romstage entry point under mainboard directory, |
| 49 | * so this one is named with prefix mainboard. |
| 50 | */ |
| 51 | void mainboard_romstage_entry(unsigned long bist) |
| 52 | { |
| 53 | sysinfo_t sysinfo; |
| 54 | int s3resume = 0; |
| 55 | int cbmem_initted; |
| 56 | u16 reg16; |
| 57 | |
| 58 | /* basic northbridge setup, including MMCONF BAR */ |
| 59 | gm45_early_init(); |
| 60 | |
| 61 | if (bist == 0) |
| 62 | enable_lapic(); |
| 63 | |
| 64 | /* First, run everything needed for console output. */ |
| 65 | i82801ix_early_init(); |
| 66 | setup_pch_gpios(&mainboard_gpio_map); |
| 67 | |
| 68 | mb_setup_lpc(); |
| 69 | |
| 70 | mb_setup_superio(); |
| 71 | |
| 72 | console_init(); |
| 73 | report_bist_failure(bist); |
| 74 | |
| 75 | reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); |
| 76 | pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); |
| 77 | if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { |
| 78 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 79 | gm45_early_reset(); |
| 80 | } |
| 81 | |
| 82 | /* ASPM related setting, set early by original BIOS. */ |
| 83 | DMIBAR16(0x204) &= ~(3 << 10); |
| 84 | |
| 85 | /* Check for S3 resume. */ |
Patrick Rudolph | ad0b482 | 2019-04-13 16:56:23 +0200 | [diff] [blame^] | 86 | s3resume = southbridge_detect_s3_resume(); |
Arthur Heymans | 3b0eb60 | 2019-01-31 22:47:09 +0100 | [diff] [blame] | 87 | |
| 88 | /* RAM initialization */ |
| 89 | enter_raminit_or_reset(); |
| 90 | memset(&sysinfo, 0, sizeof(sysinfo)); |
| 91 | get_mb_spd_addrmap(sysinfo.spd_map); |
| 92 | const struct device *dev; |
| 93 | dev = pcidev_on_root(2, 0); |
| 94 | if (dev) |
| 95 | sysinfo.enable_igd = dev->enabled; |
| 96 | dev = pcidev_on_root(1, 0); |
| 97 | if (dev) |
| 98 | sysinfo.enable_peg = dev->enabled; |
| 99 | get_gmch_info(&sysinfo); |
| 100 | |
| 101 | mb_pre_raminit_setup(&sysinfo); |
| 102 | |
| 103 | raminit(&sysinfo, s3resume); |
| 104 | |
| 105 | mb_post_raminit_setup(); |
| 106 | |
| 107 | const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); |
| 108 | /* Disable D4F0 (unknown signal controller). */ |
| 109 | pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); |
| 110 | |
| 111 | init_pm(&sysinfo, 0); |
| 112 | |
| 113 | i82801ix_dmi_setup(); |
| 114 | gm45_late_init(sysinfo.stepping); |
| 115 | i82801ix_dmi_poll_vc1(); |
| 116 | |
| 117 | MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; |
| 118 | |
| 119 | init_iommu(); |
| 120 | |
| 121 | cbmem_initted = !cbmem_recovery(s3resume); |
| 122 | |
| 123 | romstage_handoff_init(cbmem_initted && s3resume); |
| 124 | |
| 125 | printk(BIOS_SPEW, "exit main()\n"); |
| 126 | } |