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Uwe Hermann2e5a9d92008-10-12 11:58:26 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010018 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000019 */
20
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000021#include <stdint.h>
22#include <device/pci_def.h>
23#include <device/pci_ids.h>
24#include <arch/io.h>
25#include <device/pnp_def.h>
Edwin Beasanteb50c7d2010-07-06 21:05:04 +000026#include <pc80/mc146818rtc.h>
Patrick Georgi12584e22010-05-08 09:14:51 +000027#include <console/console.h>
Patrick Georgid0835952010-10-05 09:07:10 +000028#include <lib.h>
Edward O'Callaghan77757c22015-01-04 21:33:39 +110029#include <northbridge/via/cn700/raminit.h>
30#include <cpu/x86/bist.h>
Stefan Reinauerae5e11d2012-04-27 02:31:28 +020031#include "drivers/pc80/udelay_io.c"
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000032#include "lib/delay.c"
stepan836ae292010-12-08 05:42:47 +000033#include "southbridge/via/vt8237r/early_smbus.c"
Edward O'Callaghanf2920022014-04-27 00:41:50 +100034#include <superio/ite/common/ite.h>
Edward O'Callaghan5c41ee62014-04-23 01:43:38 +100035#include <superio/ite/it8716f/it8716f.h>
Uwe Hermann6dc92f02010-11-21 11:36:03 +000036#include <spd.h>
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000037
38#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
39
40static int spd_read_byte(u16 device, u16 address)
41{
42 return smbus_read_byte(device, address);
43}
44
45#include "northbridge/via/cn700/raminit.c"
46
47static const struct mem_controller ctrl = {
48 .d0f0 = 0x0000,
49 .d0f2 = 0x2000,
50 .d0f3 = 0x3000,
51 .d0f4 = 0x4000,
52 .d0f7 = 0x7000,
53 .d1f0 = 0x8000,
Uwe Hermannd773fd32010-11-20 20:23:08 +000054 .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000055};
56
Aaron Durbina0a37272014-08-14 08:35:11 -050057#include <cpu/intel/romstage.h>
Stefan Reinauer314e5512010-04-09 20:36:29 +000058void main(unsigned long bist)
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000059{
60 /* Enable multifunction for northbridge. */
61 pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
62
Edward O'Callaghanf2920022014-04-27 00:41:50 +100063 ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000064 console_init();
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000065 enable_smbus();
66 smbus_fixup(&ctrl);
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000067 report_bist_failure(bist);
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000068 ddr_ram_setup(&ctrl);
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000069}