blob: 32a853cdb30be6e75cab07ce6efc69bc438224b1 [file] [log] [blame]
Uwe Hermann2e5a9d92008-10-12 11:58:26 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000021#include <stdint.h>
22#include <device/pci_def.h>
23#include <device/pci_ids.h>
24#include <arch/io.h>
25#include <device/pnp_def.h>
26#include <arch/romcc_io.h>
27#include <arch/hlt.h>
Edwin Beasanteb50c7d2010-07-06 21:05:04 +000028#include <pc80/mc146818rtc.h>
Patrick Georgi12584e22010-05-08 09:14:51 +000029#include <console/console.h>
Stefan Reinauerc13093b2009-09-23 18:51:03 +000030#include "lib/ramtest.c"
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000031#include "northbridge/via/cn700/raminit.h"
32#include "cpu/x86/mtrr/earlymtrr.c"
33#include "cpu/x86/bist.h"
34#include "pc80/udelay_io.c"
35#include "lib/delay.c"
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000036#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
37#include "superio/ite/it8716f/it8716f_early_serial.c"
38
39#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
40
41static int spd_read_byte(u16 device, u16 address)
42{
43 return smbus_read_byte(device, address);
44}
45
46#include "northbridge/via/cn700/raminit.c"
47
48static const struct mem_controller ctrl = {
49 .d0f0 = 0x0000,
50 .d0f2 = 0x2000,
51 .d0f3 = 0x3000,
52 .d0f4 = 0x4000,
53 .d0f7 = 0x7000,
54 .d1f0 = 0x8000,
55 .channel0 = { 0x50 }, /* TODO: CN700 currently only supports 1 DIMM. */
56};
57
Stefan Reinauer314e5512010-04-09 20:36:29 +000058void main(unsigned long bist)
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000059{
60 /* Enable multifunction for northbridge. */
61 pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
62
Stefan Reinauer08670622009-06-30 15:17:49 +000063 it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Uwe Hermann2e5a9d92008-10-12 11:58:26 +000064 uart_init();
65 console_init();
66
67 enable_smbus();
68 smbus_fixup(&ctrl);
69
70 if (bist == 0)
71 early_mtrr_init();
72
73 /* Halt if there was a built-in self test failure. */
74 report_bist_failure(bist);
75
76 ddr_ram_setup(&ctrl);
77
78 /* ram_check(0, 640 * 1024); */
79}
Stefan Reinauer798ef282010-03-29 22:08:01 +000080