Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include <device/pci_ops.h> |
| 22 | #include <arch/ioapic.h> |
Timothy Pearson | 1eaaa0e | 2015-08-14 15:20:42 -0500 | [diff] [blame] | 23 | #include <lib.h> |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 24 | #include "sr5650.h" |
Timothy Pearson | 1eaaa0e | 2015-08-14 15:20:42 -0500 | [diff] [blame] | 25 | #include "cmn.h" |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 26 | |
| 27 | /* Table 6-6 Recommended Interrupt Routing Configuration */ |
| 28 | typedef struct _apic_device_info { |
| 29 | u8 group; |
| 30 | u8 swizzle; |
| 31 | u8 pin; |
| 32 | } apic_device_info; |
| 33 | |
| 34 | #define ABCD 0 |
| 35 | #define BCDA 1 |
| 36 | #define CDAB 2 |
| 37 | #define DABC 3 |
| 38 | |
| 39 | static const apic_device_info default_apic_device_info_t [] = { |
| 40 | /* Group Swizzling Port Int Pin */ |
| 41 | [0] = {0, 0, 31}, /* HT */ |
| 42 | [1] = {0, 0, 31}, /* IOMMU */ |
| 43 | [2] = {0, ABCD, 28}, /* Dev2 Grp0 [Int - 0..3] */ |
| 44 | [3] = {1, ABCD, 28}, /* Dev3 Grp1 [Int - 4..7] */ |
| 45 | [4] = {5, ABCD, 28}, /* Dev4 Grp5 [Int - 20..23] */ |
| 46 | [5] = {5, CDAB, 28}, /* Dev5 Grp5 [Int - 20..23] */ |
| 47 | [6] = {6, BCDA, 29}, /* Dev6 Grp6 [Int - 24..27] */ |
| 48 | [7] = {6, CDAB, 29}, /* Dev7 Grp6 [Int - 24..27] */ |
| 49 | [8] = {0, 0, 0 }, /* Reserved */ |
| 50 | [9] = {6, ABCD, 29}, /* Dev9 Grp6 [Int - 24..27] */ |
| 51 | [10] = {5, BCDA, 30}, /* Dev10 Grp5 [Int - 20..23] */ |
| 52 | [11] = {2, ABCD, 30}, /* Dev11 Grp2 [Int - 8..11] */ |
| 53 | [12] = {3, ABCD, 30}, /* Dev12 Grp3 [Int - 12..15] */ |
| 54 | [13] = {4, ABCD, 30} /* Dev13 Grp4 [Int - 16..19] */ |
| 55 | }; |
| 56 | |
Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 57 | /* These define names are common, so undefine them to avoid potential issues in other code */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 58 | #undef ABCD |
| 59 | #undef BCDA |
| 60 | #undef CDAB |
| 61 | #undef DABC |
| 62 | |
| 63 | /* Init APIC of sr5690 */ |
| 64 | static void sr5690_apic_init(struct device *dev) |
| 65 | { |
| 66 | u32 dword; |
| 67 | const apic_device_info *entry = default_apic_device_info_t; |
| 68 | |
| 69 | /* rpr6.2.(2). Write to the IOAPIC Features Enable register */ |
| 70 | pci_write_config32(dev, 0xF8, 0x0); |
| 71 | pci_write_config32(dev, 0xFC, 0x1F); |
| 72 | /* rpr6.2.(3). Write to the remaining interrupt routing registers */ |
| 73 | |
| 74 | /* IOAPICCMISCIND:0x3, group & swizzle of Dev 2,3,4,5 */ |
| 75 | dword = (entry[2].group | entry[2].swizzle << 4) << 0 | |
| 76 | (entry[3].group | entry[3].swizzle << 4) << 8 | |
| 77 | (entry[4].group | entry[4].swizzle << 4) << 16 | |
| 78 | (entry[5].group | entry[5].swizzle << 4) << 24; |
| 79 | pci_write_config32(dev, 0xF8, 0x3); |
| 80 | pci_write_config32(dev, 0xFC, dword); |
| 81 | |
| 82 | /* IOAPICCMISCIND:0x4, group & swizzle of Dev 6,7,9,10 */ |
| 83 | dword = (entry[6].group | entry[6].swizzle << 4) << 0 | |
| 84 | (entry[7].group | entry[7].swizzle << 4) << 8 | |
| 85 | (entry[9].group | entry[9].swizzle << 4) << 16 | |
| 86 | (entry[10].group | entry[10].swizzle << 4) << 24; |
| 87 | pci_write_config32(dev, 0xF8, 0x4); |
| 88 | pci_write_config32(dev, 0xFC, dword); |
| 89 | |
| 90 | /* IOAPICCMISCIND:0x5, group & swizzle of Dev 11,12,13 */ |
| 91 | dword = (entry[11].group | entry[11].swizzle << 4) << 0 | |
| 92 | (entry[12].group | entry[12].swizzle << 4) << 8 | |
| 93 | (entry[13].group | entry[13].swizzle << 4) << 16; |
| 94 | pci_write_config32(dev, 0xF8, 0x5); |
| 95 | pci_write_config32(dev, 0xFC, dword); |
| 96 | |
| 97 | /* IOAPICCMISCIND:0x6, pin map of dev 2,3,4,5 */ |
| 98 | dword = entry[2].pin | |
| 99 | entry[3].pin << 8 | |
| 100 | entry[4].pin << 16| |
| 101 | entry[5].pin << 24; |
| 102 | pci_write_config32(dev, 0xF8, 0x6); |
| 103 | pci_write_config32(dev, 0xFC, dword); |
| 104 | |
| 105 | /* IOAPICCMISCIND:0x7, pin map of dev 6,7,8,9 */ |
| 106 | dword = entry[6].pin | |
| 107 | entry[7].pin << 8 | |
| 108 | entry[8].pin << 16| |
| 109 | entry[9].pin << 24; |
| 110 | pci_write_config32(dev, 0xF8, 0x7); |
| 111 | pci_write_config32(dev, 0xFC, dword); |
| 112 | |
| 113 | /* IOAPICCMISCIND:0x8, pin map of dev 10,11,12,13 */ |
| 114 | dword = entry[10].pin | |
| 115 | entry[11].pin << 8 | |
| 116 | entry[12].pin << 16| |
| 117 | entry[13].pin << 24; |
| 118 | pci_write_config32(dev, 0xF8, 0x8); |
| 119 | pci_write_config32(dev, 0xFC, dword); |
| 120 | |
| 121 | /* IOAPICCMISCIND:0x9, pin map of ht, iommu */ |
| 122 | dword = entry[0].pin | entry[1].pin << 8; |
| 123 | pci_write_config32(dev, 0xF8, 0x9); |
| 124 | pci_write_config32(dev, 0xFC, dword); |
| 125 | |
| 126 | pci_write_config32(dev, 0xF8, 0x1); |
| 127 | dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; |
| 128 | /* TODO: On SR56x0/SP5100 board, the IOAPIC on SR56x0 is the |
| 129 | * 2nd one. We need to check if it also is on your board. */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 130 | setup_ioapic((void *)dword, 1); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | static void pcie_init(struct device *dev) |
| 134 | { |
| 135 | /* Enable pci error detecting */ |
| 136 | u32 dword; |
| 137 | |
| 138 | printk(BIOS_INFO, "pcie_init in sr5650_ht.c\n"); |
| 139 | |
| 140 | /* System error enable */ |
| 141 | dword = pci_read_config32(dev, 0x04); |
| 142 | dword |= (1 << 8); /* System error enable */ |
| 143 | dword |= (1 << 30); /* Clear possible errors */ |
| 144 | pci_write_config32(dev, 0x04, dword); |
| 145 | |
| 146 | /* |
| 147 | * 1 is APIC enable |
| 148 | * 18 is enable nb to accept A4 interrupt request from SB. |
| 149 | */ |
| 150 | dword = pci_read_config32(dev, 0x4C); |
| 151 | dword |= 1 << 1 | 1 << 18; /* Clear possible errors */ |
| 152 | pci_write_config32(dev, 0x4C, dword); |
| 153 | |
| 154 | sr5690_apic_init(dev); |
| 155 | } |
| 156 | |
| 157 | static void sr5690_read_resource(struct device *dev) |
| 158 | { |
Timothy Pearson | 1eaaa0e | 2015-08-14 15:20:42 -0500 | [diff] [blame] | 159 | if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { |
| 160 | printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev)); |
| 161 | set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ |
| 162 | } |
| 163 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 164 | pci_dev_read_resources(dev); |
| 165 | |
| 166 | /* rpr6.2.(1). Write the Base Address Register (BAR) */ |
Timothy Pearson | 16ff807 | 2015-12-11 12:58:07 -0600 | [diff] [blame] | 167 | pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ |
| 168 | pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 169 | |
| 170 | compact_resources(dev); |
| 171 | } |
| 172 | |
| 173 | /* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ |
| 174 | static void sr5690_set_resources(struct device *dev) |
| 175 | { |
Timothy Pearson | 16ff807 | 2015-12-11 12:58:07 -0600 | [diff] [blame] | 176 | pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ |
Timothy Pearson | 1eaaa0e | 2015-08-14 15:20:42 -0500 | [diff] [blame] | 177 | |
| 178 | if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { |
| 179 | uint32_t reg; |
| 180 | device_t amd_ht_cfg_dev; |
| 181 | device_t amd_addr_map_dev; |
| 182 | resource_t res_base; |
| 183 | resource_t res_end; |
| 184 | uint32_t base; |
| 185 | uint32_t limit; |
| 186 | struct resource *res; |
| 187 | |
| 188 | printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); |
| 189 | |
| 190 | /* Find requisite AMD CPU devices */ |
| 191 | amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0)); |
| 192 | amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); |
| 193 | |
| 194 | if (!amd_ht_cfg_dev || !amd_addr_map_dev) { |
| 195 | printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); |
| 196 | } else { |
| 197 | res = sr5650_retrieve_cpu_mmio_resource(); |
| 198 | if (res) { |
| 199 | /* Set up MMCONFIG bus range */ |
| 200 | set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */ |
| 201 | set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */ |
| 202 | set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */ |
| 203 | pci_write_config32(dev, 0x1c, res->base); |
| 204 | |
| 205 | /* Enable MMCONFIG decoding. */ |
| 206 | set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ |
| 207 | set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */ |
| 208 | set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ |
| 209 | |
| 210 | /* Set up nonposted resource in MMIO space */ |
| 211 | res_base = res->base; /* Get the base address */ |
| 212 | res_end = resource_end(res); /* Get the limit (rounded up) */ |
| 213 | printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end); |
| 214 | |
| 215 | /* Locate an unused MMIO resource */ |
| 216 | for (reg = 0xb8; reg >= 0x80; reg -= 8) { |
| 217 | base = pci_read_config32(amd_addr_map_dev, reg); |
| 218 | limit = pci_read_config32(amd_addr_map_dev, reg + 4); |
| 219 | if (!(base & 0x3)) |
| 220 | break; /* Unused resource found */ |
| 221 | } |
| 222 | |
| 223 | /* If an unused MMIO resource was available, set up the mapping */ |
| 224 | if (!(base & 0x3)) { |
| 225 | uint32_t sblk; |
| 226 | |
| 227 | /* Remember this resource has been stored. */ |
| 228 | res->flags |= IORESOURCE_STORED; |
| 229 | report_resource_stored(dev, res, " <mmconfig>"); |
| 230 | |
| 231 | /* Get SBLink value (HyperTransport I/O Hub Link ID). */ |
| 232 | sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3; |
| 233 | |
| 234 | /* Calculate the MMIO mapping base */ |
| 235 | base &= 0x000000f0; |
| 236 | base |= ((res_base >> 8) & 0xffffff00); |
| 237 | base |= 3; |
| 238 | |
| 239 | /* Calculate the MMIO mapping limit */ |
| 240 | limit &= 0x00000048; |
| 241 | limit |= ((res_end >> 8) & 0xffffff00); |
| 242 | limit |= (sblk << 4); |
| 243 | limit |= (1 << 7); |
| 244 | |
| 245 | /* Configure and enable MMIO mapping */ |
| 246 | printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit); |
| 247 | pci_write_config32(amd_addr_map_dev, reg + 4, limit); |
| 248 | pci_write_config32(amd_addr_map_dev, reg, base); |
| 249 | } |
| 250 | else { |
| 251 | printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev)); |
| 252 | } |
| 253 | } else { |
| 254 | printk(BIOS_WARNING, "%s: %s Unable to locate CPU MMCONF resource\n", __func__, dev_path(dev)); |
| 255 | } |
| 256 | } |
| 257 | } |
| 258 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 259 | pci_dev_set_resources(dev); |
| 260 | } |
| 261 | |
| 262 | static struct pci_operations lops_pci = { |
| 263 | .set_subsystem = pci_dev_set_subsystem, |
| 264 | }; |
| 265 | |
| 266 | static struct device_operations ht_ops = { |
| 267 | .read_resources = sr5690_read_resource, |
| 268 | .set_resources = sr5690_set_resources, |
| 269 | .enable_resources = pci_dev_enable_resources, |
| 270 | .init = pcie_init, |
| 271 | .scan_bus = 0, |
| 272 | .ops_pci = &lops_pci, |
| 273 | }; |
| 274 | |
| 275 | static const struct pci_driver ht_driver_sr5690 __pci_driver = { |
| 276 | .ops = &ht_ops, |
| 277 | .vendor = PCI_VENDOR_ID_ATI, |
| 278 | .device = PCI_DEVICE_ID_AMD_SR5690_HT, |
| 279 | }; |
| 280 | |
| 281 | static const struct pci_driver ht_driver_sr5670 __pci_driver = { |
| 282 | .ops = &ht_ops, |
| 283 | .vendor = PCI_VENDOR_ID_ATI, |
| 284 | .device = PCI_DEVICE_ID_AMD_SR5670_HT, |
| 285 | }; |
| 286 | |
| 287 | static const struct pci_driver ht_driver_sr5650 __pci_driver = { |
| 288 | .ops = &ht_ops, |
| 289 | .vendor = PCI_VENDOR_ID_ATI, |
| 290 | .device = PCI_DEVICE_ID_AMD_SR5650_HT, |
| 291 | }; |