amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes
Change-Id: Ia9cb4fe4f46327e38648f89da0ffce647fb118d3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12712
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c
index 6119985..b45099f 100644
--- a/src/southbridge/amd/sr5650/ht.c
+++ b/src/southbridge/amd/sr5650/ht.c
@@ -157,8 +157,8 @@
pci_dev_read_resources(dev);
/* rpr6.2.(1). Write the Base Address Register (BAR) */
- pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
- pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */
+ pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
+ pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */
compact_resources(dev);
}
@@ -166,7 +166,7 @@
/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
static void sr5690_set_resources(struct device *dev)
{
- pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
+ pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
pci_dev_set_resources(dev);
}