Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
Timothy Pearson | 5a0efd2 | 2015-06-12 20:08:29 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef SR5650_CHIP_H |
| 18 | #define SR5650_CHIP_H |
| 19 | |
| 20 | /* Member variables are defined in Config.lb. */ |
| 21 | struct southbridge_amd_sr5650_config |
| 22 | { |
| 23 | u8 gpp1_configuration; /* The configuration of General Purpose Port. */ |
| 24 | u8 gpp2_configuration; /* The configuration of General Purpose Port. */ |
| 25 | u8 gpp3a_configuration; /* The configuration of General Purpose Port. */ |
| 26 | u16 port_enable; /* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */ |
Timothy Pearson | 5a0efd2 | 2015-06-12 20:08:29 -0500 | [diff] [blame] | 27 | uint32_t pcie_settling_time; /* How long to wait after link training for PCI-e devices to |
| 28 | * initialize before probing PCI-e busses (in microseconds). |
| 29 | */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 30 | }; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 31 | |
| 32 | #endif /* SR5650_CHIP_H */ |