| Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef SR5650_CHIP_H |
| 21 | #define SR5650_CHIP_H |
| 22 | |
| 23 | /* Member variables are defined in Config.lb. */ |
| 24 | struct southbridge_amd_sr5650_config |
| 25 | { |
| 26 | u8 gpp1_configuration; /* The configuration of General Purpose Port. */ |
| 27 | u8 gpp2_configuration; /* The configuration of General Purpose Port. */ |
| 28 | u8 gpp3a_configuration; /* The configuration of General Purpose Port. */ |
| 29 | u16 port_enable; /* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */ |
| 30 | }; |
| 31 | struct chip_operations; |
| 32 | extern struct chip_operations southbridge_amd_sr5650_ops; |
| 33 | |
| 34 | #endif /* SR5650_CHIP_H */ |