blob: 85f6b13013256b631b1b1975b366348353f8d5b7 [file] [log] [blame]
Zheng Bao98fcc092011-03-27 16:39:58 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Advanced Micro Devices, Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Zheng Bao98fcc092011-03-27 16:39:58 +000015
16config SOUTHBRIDGE_AMD_SR5650
17 bool
Timothy Pearson1eaaa0e2015-08-14 15:20:42 -050018
19if SOUTHBRIDGE_AMD_SR5650
20config EXT_CONF_SUPPORT
21 bool "Enable PCI-E MMCONFIG support"
22 default y
23 help
24 Select to enable PCI-E MMCONFIG support on the SR5650.
25
26endif