southbridge/amd/sr5650: Add MCFG ACPI table support
As the southbridge largely controls the PCI[e] configuration space
this patch moves the resource allocation from the northbridge
to the southbridge when the extended configuration space region
is enabled.
Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig
index 29017c6..85f6b13 100644
--- a/src/southbridge/amd/sr5650/Kconfig
+++ b/src/southbridge/amd/sr5650/Kconfig
@@ -15,3 +15,12 @@
config SOUTHBRIDGE_AMD_SR5650
bool
+
+if SOUTHBRIDGE_AMD_SR5650
+config EXT_CONF_SUPPORT
+ bool "Enable PCI-E MMCONFIG support"
+ default y
+ help
+ Select to enable PCI-E MMCONFIG support on the SR5650.
+
+endif