huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 16 | #include <arch/io.h> |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 17 | #include <assert.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <endian.h> |
| 21 | #include <soc/addressmap.h> |
| 22 | #include <soc/spi.h> |
| 23 | #include <soc/clock.h> |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 24 | #include <spi-generic.h> |
| 25 | #include <spi_flash.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 26 | #include <stdlib.h> |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 27 | #include <timer.h> |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 28 | |
| 29 | struct rockchip_spi_slave { |
| 30 | struct spi_slave slave; |
| 31 | struct rockchip_spi *regs; |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 32 | }; |
| 33 | |
| 34 | #define SPI_TIMEOUT_US 1000 |
Julius Werner | b6092b7 | 2014-10-06 13:41:28 -0700 | [diff] [blame] | 35 | #define SPI_SRCCLK_HZ (99*MHz) |
David Hendricks | 9dceb0e | 2014-09-29 18:54:55 -0700 | [diff] [blame] | 36 | #define SPI_FIFO_DEPTH 32 |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 37 | |
| 38 | static struct rockchip_spi_slave rockchip_spi_slaves[3] = { |
| 39 | { |
| 40 | .slave = { |
| 41 | .bus = 0, |
| 42 | .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, |
| 43 | }, |
| 44 | .regs = (void *)SPI0_BASE, |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 45 | }, |
| 46 | { |
| 47 | .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, |
| 48 | .regs = (void *)SPI1_BASE, |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 49 | }, |
| 50 | { |
| 51 | .slave = { |
| 52 | .bus = 2, |
| 53 | .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, |
| 54 | }, |
| 55 | .regs = (void *)SPI2_BASE, |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 56 | }, |
| 57 | |
| 58 | }; |
| 59 | |
| 60 | static struct rockchip_spi_slave *to_rockchip_spi(struct spi_slave *slave) |
| 61 | { |
| 62 | return container_of(slave, struct rockchip_spi_slave, slave); |
| 63 | } |
| 64 | |
| 65 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) |
| 66 | { |
| 67 | assert(bus >= 0 && bus < 3); |
| 68 | return &(rockchip_spi_slaves[bus].slave); |
| 69 | } |
| 70 | |
| 71 | static void spi_cs_activate(struct spi_slave *slave) |
| 72 | { |
| 73 | struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; |
| 74 | setbits_le32(®s->ser, 1); |
| 75 | } |
| 76 | |
| 77 | static void spi_cs_deactivate(struct spi_slave *slave) |
| 78 | { |
| 79 | struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; |
| 80 | clrbits_le32(®s->ser, 1); |
| 81 | } |
| 82 | |
| 83 | static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable) |
| 84 | { |
| 85 | if (enable == 1) |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 86 | write32(®s->spienr, 1); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 87 | else |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 88 | write32(®s->spienr, 0); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) |
| 92 | { |
Julius Werner | 97ab425 | 2015-03-24 16:12:08 -0700 | [diff] [blame] | 93 | unsigned short clk_div = SPI_SRCCLK_HZ / hz; |
| 94 | assert(clk_div * hz == SPI_SRCCLK_HZ && !(clk_div & 1)); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 95 | write32(®s->baudr, clk_div); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 96 | } |
| 97 | |
David Hendricks | b4ff291 | 2014-09-29 13:48:40 -0700 | [diff] [blame] | 98 | void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 99 | { |
David Hendricks | 9dceb0e | 2014-09-29 18:54:55 -0700 | [diff] [blame] | 100 | struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 101 | unsigned int ctrlr0 = 0; |
| 102 | |
| 103 | rkclk_configure_spi(bus, SPI_SRCCLK_HZ); |
| 104 | rockchip_spi_enable_chip(regs, 0); |
David Hendricks | b4ff291 | 2014-09-29 13:48:40 -0700 | [diff] [blame] | 105 | rockchip_spi_set_clk(regs, speed_hz); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 106 | |
| 107 | /* Operation Mode */ |
| 108 | ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET); |
| 109 | |
| 110 | /* Data Frame Size */ |
| 111 | ctrlr0 |= SPI_DFS_8BIT << SPI_DFS_OFFSET; |
| 112 | |
| 113 | /* Chip Select Mode */ |
| 114 | ctrlr0 |= (SPI_CSM_KEEP << SPI_CSM_OFFSET); |
| 115 | |
| 116 | /* SSN to Sclk_out delay */ |
| 117 | ctrlr0 |= (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET); |
| 118 | |
| 119 | /* Serial Endian Mode */ |
| 120 | ctrlr0 |= (SPI_SEM_LITTLE << SPI_SEM_OFFSET); |
| 121 | |
| 122 | /* First Bit Mode */ |
| 123 | ctrlr0 |= (SPI_FBM_MSB << SPI_FBM_OFFSET); |
| 124 | |
| 125 | /* Byte and Halfword Transform */ |
| 126 | ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET); |
| 127 | |
| 128 | /* Rxd Sample Delay */ |
| 129 | ctrlr0 |= (0 << SPI_RXDSD_OFFSET); |
| 130 | |
| 131 | /* Frame Format */ |
| 132 | ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); |
| 133 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 134 | write32(®s->ctrlr0, ctrlr0); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 135 | |
David Hendricks | 9dceb0e | 2014-09-29 18:54:55 -0700 | [diff] [blame] | 136 | /* fifo depth */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 137 | write32(®s->txftlr, SPI_FIFO_DEPTH / 2 - 1); |
| 138 | write32(®s->rxftlr, SPI_FIFO_DEPTH / 2 - 1); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | int spi_claim_bus(struct spi_slave *slave) |
| 142 | { |
| 143 | spi_cs_activate(slave); |
| 144 | return 0; |
| 145 | } |
| 146 | |
| 147 | void spi_release_bus(struct spi_slave *slave) |
| 148 | { |
| 149 | spi_cs_deactivate(slave); |
| 150 | } |
| 151 | |
| 152 | static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) |
| 153 | { |
Aaron Durbin | a32a9d1 | 2014-09-24 09:53:15 -0500 | [diff] [blame] | 154 | struct stopwatch sw; |
| 155 | |
| 156 | stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_US); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 157 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 158 | if (!(read32(®s->sr) & SR_BUSY)) |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 159 | return 0; |
Aaron Durbin | a32a9d1 | 2014-09-24 09:53:15 -0500 | [diff] [blame] | 160 | } while (!stopwatch_expired(&sw)); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 161 | printk(BIOS_DEBUG, |
| 162 | "RK SPI: Status keeps busy for 1000us after a read/write!\n"); |
| 163 | return -1; |
| 164 | } |
| 165 | |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 166 | static void set_tmod(struct rockchip_spi *regs, unsigned int tmod) |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 167 | { |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 168 | clrsetbits_le32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, |
| 169 | tmod << SPI_TMOD_OFFSET); |
| 170 | } |
| 171 | |
| 172 | static void set_transfer_mode(struct rockchip_spi *regs, |
| 173 | unsigned int sout, unsigned int sin) |
| 174 | { |
| 175 | if (!sin && !sout) |
| 176 | return; |
| 177 | else if (sin && sout) |
| 178 | set_tmod(regs, SPI_TMOD_TR); /* tx and rx */ |
| 179 | else if (!sin) |
| 180 | set_tmod(regs, SPI_TMOD_TO); /* tx only */ |
| 181 | else if (!sout) |
| 182 | set_tmod(regs, SPI_TMOD_RO); /* rx only */ |
| 183 | } |
| 184 | |
| 185 | /* returns 0 to indicate success, <0 otherwise */ |
| 186 | static int do_xfer(struct spi_slave *slave, const void *dout, |
| 187 | unsigned int *bytes_out, void *din, unsigned int *bytes_in) |
| 188 | { |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 189 | struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 190 | uint8_t *in_buf = din; |
| 191 | uint8_t *out_buf = (uint8_t *)dout; |
| 192 | unsigned int min_xfer; |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 193 | |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 194 | if (*bytes_out == 0) |
| 195 | min_xfer = *bytes_in; |
| 196 | else if (*bytes_in == 0) |
| 197 | min_xfer = *bytes_out; |
| 198 | else |
| 199 | min_xfer = MIN(*bytes_in, *bytes_out); |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 200 | |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 201 | while (min_xfer) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 202 | uint32_t sr = read32(®s->sr); |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 203 | int xferred = 0; /* in either (or both) directions */ |
| 204 | |
| 205 | if (*bytes_out && !(sr & SR_TF_FULL)) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 206 | write32(®s->txdr, *out_buf); |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 207 | out_buf++; |
| 208 | *bytes_out -= 1; |
| 209 | xferred = 1; |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 210 | } |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 211 | |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 212 | if (*bytes_in && !(sr & SR_RF_EMPT)) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 213 | *in_buf = read32(®s->rxdr) & 0xff; |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 214 | in_buf++; |
| 215 | *bytes_in -= 1; |
| 216 | xferred = 1; |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 217 | } |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 218 | |
| 219 | min_xfer -= xferred; |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 220 | } |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 221 | |
| 222 | if (rockchip_spi_wait_till_not_busy(regs)) { |
| 223 | printk(BIOS_ERR, "Timed out waiting on SPI transfer\n"); |
| 224 | return -1; |
| 225 | } |
| 226 | |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 227 | return 0; |
| 228 | } |
| 229 | |
Patrick Georgi | 13cee14 | 2015-04-14 12:52:08 +0200 | [diff] [blame] | 230 | unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) |
| 231 | { |
| 232 | return min(65535, buf_len); |
| 233 | } |
| 234 | |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 235 | int spi_xfer(struct spi_slave *slave, const void *dout, |
| 236 | unsigned int bytes_out, void *din, unsigned int bytes_in) |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 237 | { |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 238 | struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; |
| 239 | int ret = 0; |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 240 | |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 241 | /* |
| 242 | * RK3288 SPI controller can transfer up to 65536 data frames (bytes |
| 243 | * in our case) continuously. Break apart large requests as necessary. |
| 244 | * |
| 245 | * FIXME: And by 65536, we really mean 65535. If 0xffff is written to |
| 246 | * ctrlr1, all bytes that we see in rxdr end up being 0x00. 0xffff - 1 |
| 247 | * seems to work fine. |
| 248 | */ |
| 249 | while (bytes_out || bytes_in) { |
| 250 | unsigned int in_now = MIN(bytes_in, 0xffff); |
| 251 | unsigned int out_now = MIN(bytes_out, 0xffff); |
| 252 | unsigned int in_rem, out_rem; |
| 253 | |
| 254 | rockchip_spi_enable_chip(regs, 0); |
| 255 | |
| 256 | /* Enable/disable transmitter and receiver as needed to |
| 257 | * avoid sending or reading spurious bits. */ |
| 258 | set_transfer_mode(regs, bytes_out, bytes_in); |
| 259 | |
| 260 | /* MAX() in case either counter is 0 */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 261 | write32(®s->ctrlr1, MAX(in_now, out_now) - 1); |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 262 | |
| 263 | rockchip_spi_enable_chip(regs, 1); |
| 264 | |
| 265 | in_rem = in_now; |
| 266 | out_rem = out_now; |
| 267 | ret = do_xfer(slave, dout, &out_rem, din, &in_rem); |
| 268 | if (ret < 0) |
| 269 | break; |
| 270 | |
| 271 | if (bytes_out) { |
| 272 | unsigned int sent = out_now - out_rem; |
| 273 | bytes_out -= sent; |
| 274 | dout += sent; |
| 275 | } |
| 276 | |
| 277 | if (bytes_in) { |
| 278 | unsigned int received = in_now - in_rem; |
| 279 | bytes_in -= received; |
| 280 | din += received; |
| 281 | } |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 282 | } |
David Hendricks | 558614d | 2014-09-12 18:58:47 -0700 | [diff] [blame] | 283 | |
| 284 | rockchip_spi_enable_chip(regs, 0); |
| 285 | return ret < 0 ? ret : 0; |
huang lin | 630c86d | 2014-08-26 17:28:46 +0800 | [diff] [blame] | 286 | } |